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copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 june, 2006 pex 8111bb expresslane pci express-to-pci bridge data book version 1.2 june 2006 website www.plxtech.com technical support www.plxtech.com/support phone 408 774-9060 800 759-3735 fax 408 774-2169
copyright information copyright ? 2005 ? 2006 plx technology, inc. all rights reserved. the information in this document is proprietary to plx technology. no part of this doc ument may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from plx technology. plx technology provides this documentation withou t warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. while the information contained herein is believed to be accurate, such information is pr eliminary, and no representations or warranties of accuracy or completeness are made. in no event will plx technology be liable for damages arising directly or indirectly from any us e of or reliance upon the informati on contained in this document. plx technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. plx technology retains the right to make changes to this product at any time, without notice. products may have minor variations to this publication, known as errata. plx technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of plx technology products. plx technology and the plx logo are registered tr ademarks and expresslane is a trademark of plx technology, inc. pci express is a trademark of the pci special interest group. all product names are trademarks, re gistered trademarks, or servicem arks of their respective owners. order number: 8111bb-sil-db-p1-1.2 june, 2006 plx technology, inc. ii pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
june, 2006 revision history pex 8111bb expresslane pci express-to-pci bridge data book iii copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 revision history version date description of changes 1.0 november, 2005 initial productio n release silic on revision bb. 1.1 december, 2005 table 16-2 ? corrected jtag idcode values in version column. table 17-1 ? removed ?ambient temperature? row. table 18-2 ? corrected 161-ball fb ga package ball pitch dimension. global (2 places) ? changed ?pci express host? to ?pci express root complex.? section 5.1.1.2 ? added note regarding no snoop and relaxed ordering bits. register 14-56, (offset 68h; devctl) pci express device control, bits [3:0] ? added ?valid only in forwar d bridge mode? to bit descriptions. register 14-82, (offset 101ch; po wer) power ? added ?(forward bridge mode only? to register title. figure 18-3 ? corrected title. 1.2 june, 2006 reorganized chapter 2, ?ball descriptions.? other changes include: ? clarified reset for gpio[3:2] in forward and reverse modes. wakein# definition, added ?in forward bridge mode, pull wakein# high.? idsel definitions, replaced ?in forward bridge mode, idsel is grounded or pulled up to 3.3v? with ?it is recommended to ground idsel in forward bridge mode to prevent it from floating.? pcirst# definitions, changed ?od? to ?tp?. pclko definitions, added ?pclko can be connected to pclki to drive pclki.? global ? corrected pme# refere nces to pmein# and pmeout#. global ? corrected pex_perst# references to perst#. section 4.1.1.1, replaced last two sentences of second paragraph with ?pcirst# is asserted for at least 2 ms after the power levels are valid.? added new chapter 9, ?bridge operation,? and renumbered all subsequent chapters. corrected table 18-2 (formerly table 16-2) ve rs io n column values to reflect bb silicon revision. registers split into two chapters ? one for forward bridge mode (chapter 15), the other for reverse bridge mode (chapter 16). register chapters, pci control register, bit 26, ch anged first sentence describing action when cleared. chapter 19, ?electrical specifications,? changes (formerly chapter 17): replaced sections 19.1 and 19.2 with section 19.1, ?power sequence,? and section 19.1.1, ?vio.? added new table 19-2, ?packa ge thermal resistance,? and renumbered all s ubsequent tables. added section 19.4.2, ?serdes interface dc characteristics.? corrected vdd3.3 si gnal reference in table 19-4 for v ih . changed ?tlb? references to ?tlp?. miscellaneous change s for readability. miscellaneous corrections.
data book plx technology, inc. iv pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 preface this document contains material that is propriet ary to plx. reproduction without the express written consent of plx is prohibited. all reasonable attempts are made to ensure the co ntents of this document are accurate; however no liability, expressed or implie d is guaranteed. plx rese rves the right to modify this document, without notification, at any time. this plx document is periodically updated as new information is made available. scope this document describes the pex 8111 bridge operation and provides operational data for customer use. audience this data book provides the functional details of plx technology expresslane tm pex 8111 pci express-to-pci bridge, for hardware de signers and software/firmware engineers. supplemental documentation this data book assumes that the reader is familiar with the documents referenced below. plx technology, inc. 870 maude ave., sunnyvale, ca 94085 usa tel: 408 774-9060 or 800 759-3735, fax: 408 774-2169 , http://www.plxtech.com ? pex 8111 quick start design note pci special interest group (pci-sig) 3855 sw 153rd drive, beaverton, or 97006 usa tel: 503 619-0569, fax: 503 644-6708, http://www.pcisig.com ? pci local bus specification, revision 3.0 ? pci local bus specification, revision 2.2 ? pci to pci bridge architecture specification, revision 1.1 ? pci bus power management interface specification, revision 1.1 ? pci express base specification, revision 1.0a ? pci express to pci/pci-x bridge specification, revision 1.0 ? pci express card electromechanical (cem) specification, revision 1.0a the institute of electrical a nd electronics engineers, inc. 445 hoes lane, po box 1331, piscataway, nj 08855-1331, usa tel: 800 678-4333 (domestic only) or 732 981-0060, fax: 732 981-1721, http://www.ieee.org ? ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture, 1990 ? ieee 1149.1a-1993, ieee stand ard test access port and boundary-scan architecture ? ieee standard 1149.1b-1994, specifications for ven dor-specific extensions
june, 2006 supplemental documentation abbreviations pex 8111bb expresslane pci express-to-pci bridge data book v copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 supplemental document ation abbreviations note: in this data book, shortened titles are provided to the previously listed documents. the following table lists these abbreviations. data assignment conventions abbreviation document pci r3.0 pci local bus specification, revision 3.0 pci r2.2 pci local bus specification, revision 2.2 pci-to-pci bridge r1.1 pci to pci bridge architecture specification, revision 1.1 pci power mgmt. r1.1 pci bus power manageme nt interface specifi cation, revision 1.1 pci express r1.0a pci express ba se specification, revision 1.0a pci express-to-pci/ pci-x bridge r1.0 pci express to pci/pci-x bridge specification, revision 1.0 ieee standard 1149.1-1990 ieee st andard test access port and boundary-scan architecture data width pex 8111 convention 1 byte (8 bits) byte 2 bytes (16 bits) word 4 bytes (32 bits) dword/dword/dword
data book plx technology, inc. vi pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 terms and abbreviations the following table lists common terms and abbreviations used in this document. terms and abbreviations defined in the pci express r1.0a are not included in this table. terms and abbreviations terms and abbreviations definition # indicates an active-low signal. ack acknowledge control packet. a contro l packet used by a destination to acknowledge data pack et receipt. a signal that acknowledges the signal receipt. adb allowable disconnect boundary. adq allowable disconnect quantity. in pc i express, the adq is a buffer size. used to indicate memory re quirements or reserves. bar base address register. byte 8-bit quantity of data. ca completion with completer abort status. cfg access initiated by pci configur ation transactions on the primary bus. clock cycle one period of the pci bus clock. completer device addressed by a requester . crs configuration retry status. csr configuration status register; control and status register; command and status register dac dual address cycle. a pci transaction wherein a 64-bit address is transferred across a 32-bit data path in two clock cycles. destination bus target of a transact ion that crosses a bri dge is said to reside on the destination bus. dllp data link layer packet (originates at the data link la yer); can contain flow control (fcx dllps) acknowle dge packets (ack and nak dllps); and power manageme nt (pmx dllps). downstream transactions that are forwarded from the primary bus to the secondary bus of a bridge are said to be flowing downstream. dword 32-bit quantity of data. ecrc end-to-end cyclic redundancy check (crc) ee access initiated by the serial eeprom controller during initialization. endpoints devices, other than the root co mplex and switches, that are requesters or completers of pci express transactions. endpoints can be pci express endpoints or legacy endpoints. legacy endpoints can support i/o and lo cked transaction semantics. pci express endpoints do not support i/o and locked transaction semantics. fcp flow control packet devices on each link exchange fcps, which carry header and data payload credit information for one of thre e packet types ? posted requests, non-posted requests, and completions. forward bridge mode the primary bus is cl osest to the pci express root complex. host computer that provides services to computers that connect to it on a network. considered to be in charge of the other devices connected to the bus.
june, 2006 terms and abbreviations pex 8111bb expresslane pci express-to-pci bridge data book vii copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 hwinit hardware initialized register or register bit. the register bits are initialized by a pex 8111 hardware initia lization mechanism or pex 8111 serial eeprom register initialization feature. register bits are read -only after initialization and are reset only with a cold or warm reset. i cmos input. i/o cmos bi-directional input output. lane differential signal pair in each direction. layers pci express defines three layers: transaction layer ? the primary function of the transaction layer is assembly and disassembly of tlps. th e major components of a transaction layer packet (tlp) are header, data pa yload, and an optional digest field. data link layer ? the primary task of the data link layer is to provide link management and data inte grity, including error detect ion and correction. this layer defines the data control for pci express. physical layer ? the primary value to users is that this layer appears to the upper layers to be pci. it connects the lower protocols to the upper layers. mm access initiated by pci memory transa ctions on the primary or secondary bus, using the address range defined by pci base address 0 . msi message signaled interrupt. nak negative acknowledge. non-posted transaction a memory re ad, i/o read or write, or configuration read or write that returns a completion to the master. ns no snoop. o cmos output. od open drain output. originating bus master of a transacti on that crosses a bridge is said to reside on the originating bus. packet types there are three packet types: tlp , transaction layer packet dllp , data link layer packet plp , physical layer packet pci pci compliant pci peripheral component inte rconnect. a pci bus is a high-performance bus that is 32 bits or 64 bits wide. it is designed to be used with devices that contain high-bandwidth requirements ( such as , the display subsystem). it is an i/o bus that has the ability to be dynamically configured. pci master (initiator) drives the addres s phase and transact ion boundary (frame#). initiates a transaction and dr ives data handshaking (ir dy#) with the target. pci target claims the transaction by asserting devsel# and handshakes the transaction (trdy#) with the initiator. pci transaction read, write, read burst, or write burst operation on the pci bus. includes an address phase, followed by one or more data phases. pci transfer during a transfer, data is moved from the source to the destination on the pci bus. trdy# and irdy# assertion indicates a data transfer. pcie pci express. terms and abbreviations (cont.) terms and abbreviations definition
data book plx technology, inc. viii pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 port interface between a pc i express component and the link . consists of transmitters and receivers. an ingress port receives a packet. an egress port transmits a packet. a link is a physical connection between two devices that consists of x n lanes . an x1 link consists of one transmit and one receive signal, where each signal is a differential pair. this is one lane. there are four lines or signals in an x1 link. posted transaction memory write that does not return a completion to the master. primary bus bus closest to the pci express r oot complex (forward bridge mode) or the pci host cpu (reverse bridge mode). pu signal is internally pulled up. qos quality of service. rc root complex. rcb read boundary completion. request packet a non-posted request packet transmitted by a requester has a completion packet returned by the associated completer. a posted request packet transmitted by a requester has no completion packet returned by the completer. requester device that originates a transaction or puts a transaction sequence into the pci express fabric. reverse bridge mode the primary bus is closest to the pci host cpu. ro read-only register or register bit. re gister bits are read -only and cannot be altered by software. register bits ar e initialized by a pex 8111 hardware initialization mechanism or pex 8111 serial eeprom register initialization feature. ro relaxed ordering. rsvdp reserved and preserved. reserved for future rw implementations. registers are read-only and must return 0 when read. software must preserve value read for writes to bits. rsvdz reserved and zero. reserved for future rw1c implementations. registers are read-only and must return 0 when read. software must use 0 for writes to bits. terms and abbreviations (cont.) terms and abbreviations definition !$ifferential0air !$ifferential0air ineachdirection one ,ane 4hisisan x,ink 4herearefoursignals
june, 2006 terms and abbreviations pex 8111bb expresslane pci express-to-pci bridge data book ix copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 rw read-write register. register bits are read -write and set or cleared by software to the needed state. rw1c read-only status. write 1 to clear status re gister. register bits indicate status when read; a set bit indicating a status event is cleared by writing 1. writing 0 to rw1c bits has no effect. rx received packet. sc successful completion. secondary bus the bus farthest from the pci e xpress root complex (forward bridge mode) or the pci host cpu (rev erse bridge mode). strap strapping pads ( such as , bar0enb#, forward, and extarb) must be connected to h or l on the board. sts sustained three-state output, driven high for one clk before float. tc traffic class. tlp translation layer packet. tp totem pole. ts three-state bi-directional. tx transmitted packet. upstream transactions that are forwarded fro m the secondary bus to the primary bus of a bridge are said to be flowing upstream. ur unsupported request. vc virtual channel. wo write-only register. used to indicate that a register is written by the serial eeprom controller. word 16-bit quantity of data. terms and abbreviations (cont.) terms and abbreviations definition
data book plx technology, inc. x pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book xi copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1 pci express endpoint interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.2 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.3 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.4 data transfer pathways . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 chapter 2 ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 ball description abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 pci signal pull-up resistors (forward bridge mode only) . . . . . . . . . . . . . . . . . . . . . 5 2.3 ball description ? 144-ball pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.1 pci express signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.2 pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.3 clock, reset, and miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.4 jtag interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.5 test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.6 no connect signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.7 power and ground signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.8 ball tables ? 144-ball pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.9 physical ball assignment ? 144-ball pbga package . . . . . . . . . . . . . . . . . . . 16 2.4 ball description ? 161-ball fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.1 pci express signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.3 clock, reset, and miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.4 jtag interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.5 test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.6 no connect signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.7 power and ground signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.8 ball tables ? 161-ball fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.9 physical ball assignment ? 161-ball fbga package . . . . . . . . . . . . . . . . . . . 29 chapter 3 reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 3.1 forward bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 reverse bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3 initialization summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 chapter 4 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 forward bridge initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.1 forward bridge reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.1.1 fundamental reset (cold/warm reset) . . . . . . . . . . . . . . . . . . . . . 33 4.1.1.2 primary reset due to physical layer mechanism (hot reset) . . . . 33 4.1.1.3 primary reset due to data link down . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.1.4 secondary bus reset by way of bridge control register . . . . . . . . 34 4.1.1.5 bus parking during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 reverse bridge initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.1 reverse bridge reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.2 reverse bridge secondary bus reset by way of bridge control register . . . 35
contents plx technology, inc. xii pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.1 forward bridge pci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.1.1 forward bridge internally generated interrupts . . . . . . . . . . . . . . . . . . . . . . . 37 5.1.1.1 virtual wire interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.1.2 message signaled interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 reverse bridge pci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.1 reverse bridge internally generated interrupts . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.1.1 intx# signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.1.2 message signaled interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 chapter 6 serial eeprom controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2 serial eeprom data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.4 serial eeprom random read/write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4.1 serial eeprom opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4.2 serial eeprom low-level acce ss routines . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4.3 serial eeprom read status routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4.4 serial eeprom write data routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.4.5 serial eeprom read da ta routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 chapter 7 address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2 i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2.1 enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2.2 i/o base and limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2.3 isa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.4 vga mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2.4.1 vga palette snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.3 memory-mapped i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.3.1 enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.3.2 memory base and limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.3.3 vga mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.4 prefetchable space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.4.1 enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.4.2 prefetchable base and limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.4.3 64-bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4.3.1 forward bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4.3.2 reverse bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.4.4 vga mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 chapter 8 configuration transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.2 type 0 configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3 type 1 configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.4 type 1-to-type 0 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.4.1 forward bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.4.2 reverse bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.5 type 1-to-type 1 forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.5.1 forward bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.5.2 reverse bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.6 type 1-to-special cycle forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
june, 2006 contents pex 8111bb expresslane pci express-to-pci bridge data book xiii copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8.7 pci express enhanced configuration mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.7.1 memory-mapped indirect (reverse bridge mode only) . . . . . . . . . . . . . . . . . 63 8.8 configuration retry mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.8.1 forward bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.8.2 reverse bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 chapter 9 bridge operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1 forward bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.1 forward bridge flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.1.2 forward bridge buffer size and management . . . . . . . . . . . . . . . . . . . . . . . . 66 9.1.3 forward bridge requester id and tag assignment . . . . . . . . . . . . . . . . . . . . 66 9.1.4 forward bridge pci express-to-pci forwarding (downstream) . . . . . . . . . . . 67 9.1.4.1 transaction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.1.4.2 write transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.1.4.3 read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.1.5 forward bridge pci-to-pci express forwarding (upstream) . . . . . . . . . . . . . 73 9.1.5.1 transaction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.1.5.2 write decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.1.5.3 read decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.1.5.4 pci express header field formation rules . . . . . . . . . . . . . . . . . . . 74 9.1.5.5 requester id and tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.1.5.6 memory write or memory write and invalidate . . . . . . . . . . . . . . . . 75 9.1.5.7 delayed transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.5.8 memory read, memory read line, or memory read line multiple . 76 9.1.5.9 i/o write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.1.5.10 i/o read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.1.6 forward bridge pci transaction terminations . . . . . . . . . . . . . . . . . . . . . . . . 79 9.1.6.1 pci master termination initiated by pex 8111 . . . . . . . . . . . . . . . . 80 9.1.6.2 pci master abort received by pex 8111 . . . . . . . . . . . . . . . . . . . . 80 9.1.6.3 delayed write target termination response . . . . . . . . . . . . . . . . . 81 9.1.6.4 posted write target termination response . . . . . . . . . . . . . . . . . . 81 9.1.6.5 delayed read target termination response . . . . . . . . . . . . . . . . . 82 9.1.6.6 target retry initiated by pex 8111 . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.1.6.7 target disconnect initiated by pex 8111 . . . . . . . . . . . . . . . . . . . . . 83 9.1.6.8 target abort initiated by pex 8111 . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.2 reverse bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.2.1 reverse bridge pci-to-pci express forwarding (downstream) . . . . . . . . . . 85 9.2.1.1 transaction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 chapter 10 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.1 forward bridge error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.1.1 forward bridge pci express originating interface (primary to secondary) . 87 10.1.1.1 received poisoned tlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.1.1.2 pci uncorrectable data errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.1.1.3 pci address errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.1.1.4 pci master abort on posted transaction . . . . . . . . . . . . . . . . . . . . 89 10.1.1.5 pci master abort on non-posted transaction . . . . . . . . . . . . . . . . 89 10.1.1.6 pci target abort on posted transaction . . . . . . . . . . . . . . . . . . . . 90 10.1.1.7 pci target abort on non-posted transaction . . . . . . . . . . . . . . . . 90 10.1.1.8 pci retry abort on posted transaction . . . . . . . . . . . . . . . . . . . . . 90 10.1.1.9 pci retry abort on non-posted transaction . . . . . . . . . . . . . . . . . 90
contents plx technology, inc. xiv pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.1.2 forward bridge pci originating interface (secondary to primary) . . . . . . . . 91 10.1.2.1 received pci errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.1.2.2 unsupported request (ur) completion status . . . . . . . . . . . . . . . 93 10.1.2.3 completer abort (ca) completion status . . . . . . . . . . . . . . . . . . . . 93 10.1.3 forward bridge timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.1.3.1 pci express completion timeout errors . . . . . . . . . . . . . . . . . . . . 94 10.1.3.2 pci delayed transaction timeout errors . . . . . . . . . . . . . . . . . . . . 94 10.1.4 forward bridge ?other? errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.2 reverse bridge error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.2.1 reverse bridge pci express originating interface (secondary to primary) . 95 10.2.1.1 received poisoned tlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.2.1.2 pci uncorrectable data errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.2.1.3 pci address errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.2.1.4 pci master abort on posted transaction . . . . . . . . . . . . . . . . . . . . 96 10.2.1.5 pci master abort on non-posted transaction . . . . . . . . . . . . . . . . 97 10.2.1.6 pci target abort on posted transaction . . . . . . . . . . . . . . . . . . . . 97 10.2.1.7 pci target abort on non-posted transaction . . . . . . . . . . . . . . . . 97 10.2.1.8 pci retry abort on posted transaction . . . . . . . . . . . . . . . . . . . . . 97 10.2.1.9 pci retry abort on non-posted transaction . . . . . . . . . . . . . . . . . 97 10.2.2 reverse bridge pci originating interface (primary to secondary) . . . . . . . . 98 10.2.2.1 received pci errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.2.2.2 unsupported request (ur) completion status . . . . . . . . . . . . . . 100 10.2.2.3 completer abort (ca) completion status . . . . . . . . . . . . . . . . . . . 100 10.2.3 reverse bridge timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.2.3.1 pci express completion timeout errors . . . . . . . . . . . . . . . . . . . 100 10.2.3.2 pci delayed transaction timeout errors . . . . . . . . . . . . . . . . . . . 100 10.2.4 reverse bridge pci express error messages . . . . . . . . . . . . . . . . . . . . . . 101 10.2.5 reverse bridge ?other? errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 chapter 11 exclusive (locked) access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 11.1 forward bridge exclusive accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.1.1 forward bridge lock sequence across pex 8111 . . . . . . . . . . . . . . . . . . . 103 11.1.2 forward bridge pci master rules for supporting lock# . . . . . . . . . . . . . 104 11.1.3 forward bridge acquiring exclusive access across pex 8111 . . . . . . . . . 104 11.1.4 forward bridge non-posted transactions and lock . . . . . . . . . . . . . . . . . . 104 11.1.5 forward bridge continuing exclusive access . . . . . . . . . . . . . . . . . . . . . . . 104 11.1.6 forward bridge completing exclusive access . . . . . . . . . . . . . . . . . . . . . . 104 11.1.7 forward bridge invalid pci express requests while locked . . . . . . . . . . . 105 11.1.8 forward bridge locked transaction originating on pci bus . . . . . . . . . . . 105 11.1.9 forward bridge pci bus errors while locked . . . . . . . . . . . . . . . . . . . . . . . 105 11.1.9.1 pci master abort during posted transaction . . . . . . . . . . . . . . . . 105 11.1.9.2 pci master abort during non-posted transaction . . . . . . . . . . . . 105 11.1.9.3 pci target abort during posted transaction . . . . . . . . . . . . . . . . 105 11.1.9.4 pci target abort during non-posted transaction . . . . . . . . . . . . 105 11.2 reverse bridge exclusive accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.2.1 reverse bridge pci target rules for supporting lock# . . . . . . . . . . . . . . 106 11.2.2 reverse bridge acquiring exclusive ac cess across pex 8111 . . . . . . . . . 106 11.2.3 reverse bridge completing exclusive access . . . . . . . . . . . . . . . . . . . . . . 106 11.2.4 reverse bridge pci express locked read request . . . . . . . . . . . . . . . . . 106 11.2.5 reverse bridge limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
june, 2006 contents pex 8111bb expresslane pci express-to-pci bridge data book xv copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 12 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.1 forward bridge power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.1.1 forward bridge link state power management . . . . . . . . . . . . . . . . . . . . . 107 12.1.1.1 link power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.1.1.2 link state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.1.2 forward bridge power management states . . . . . . . . . . . . . . . . . . . . . . . . 109 12.1.2.1 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.1.3 forward bridge power management signaling . . . . . . . . . . . . . . . . . . . . . . 110 12.1.4 set slot power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.2 reverse bridge power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.2.1 reverse bridge active state power management (aspm) . . . . . . . . . . . . 111 12.2.1.1 aspm states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.2.2 reverse bridge power management states . . . . . . . . . . . . . . . . . . . . . . . . 112 12.2.2.1 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.2.3 reverse bridge power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.2.4 reverse bridge pmeout# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.2.5 reverse bridge set slot power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 chapter 13 pci express messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1 forward bridge pci express messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1.1 forward bridge intx# interrupt signaling . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1.2 forward bridge power management messages . . . . . . . . . . . . . . . . . . . . . 115 13.1.3 forward bridge error signaling messages . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1.4 forward bridge locked transactions support . . . . . . . . . . . . . . . . . . . . . . 116 13.1.5 forward bridge slot power limit support . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.1.6 forward bridge hot plug signaling messages . . . . . . . . . . . . . . . . . . . . . . 116 13.2 reverse bridge pci express messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.2.1 reverse bridge intx# interrupt message support . . . . . . . . . . . . . . . . . . . 117 13.2.2 reverse bridge power management message support . . . . . . . . . . . . . . . 117 13.2.2.1 pme handling requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.2.3 reverse bridge error signaling message support . . . . . . . . . . . . . . . . . . . 117 13.2.4 reverse bridge locked transaction support . . . . . . . . . . . . . . . . . . . . . . . 117 13.2.5 reverse bridge slot power limit support . . . . . . . . . . . . . . . . . . . . . . . . . . 117 chapter 14 pci arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 19 14.2 internal arbiter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.2.1 single-level mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.2.2 multi-level mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.3 external arbiter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 14.4 arbitration parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 chapter 15 forward bridge mode configuration registers . . . . . . . . . . . . . . . . . . . . . . . . 121 15.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 15.1.1 indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 15.2 configuration access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 15.3 register attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 15.4 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 15.5 register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 15.5.1 pci-compatible configuration registers (type 1) . . . . . . . . . . . . . . . . . . . 124 15.5.2 pci-compatible exte nded capability registers fo r pci express interface 125 15.5.3 pci express extended capab ility registers . . . . . . . . . . . . . . . . . . . . . . . . 126 15.5.4 main control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
contents plx technology, inc. xvi pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.6 pci-compatible configuration registers (type 1) . . . . . . . . . . . . . . . . . . . . . . . . . 128 15.7 pci-compatible extended capability registers for pci express interface . . . . . . 145 15.8 pci express extended capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.8.1 pci express power budgeting registers . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.8.2 pci express serial number registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.9 main control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 chapter 16 reverse bridge mode configuration registers . . . . . . . . . . . . . . . . . . . . . . . . .181 16.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.1.1 indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.2 configuration access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.3 register attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.4 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.5 register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.5.1 pci-compatible configuration registers (type 1) . . . . . . . . . . . . . . . . . . . 184 16.5.2 pci-compatible exten ded capability registers for pc i express interface . 185 16.5.3 pci express extended capab ility registers . . . . . . . . . . . . . . . . . . . . . . . . 186 16.5.4 main control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.6 pci-compatible configuration registers (type 1) . . . . . . . . . . . . . . . . . . . . . . . . . 188 16.7 pci-compatible extended capability registers for pci express interface . . . . . . 204 16.8 pci express extended capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16.8.1 pci express power budgeting registers . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16.8.2 pci express serial number registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 16.9 main control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 chapter 17 shared memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 41 17.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 41 17.2 serial eeprom accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.3 pci express accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.4 pci accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 chapter 18 testability and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 18.1 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 18.1.1 ieee standard 1149.1 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . 243 18.1.2 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 18.1.3 jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 18.1.4 jtag reset input trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 chapter 19 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 19.1 power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 19.1.1 vio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 19.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 19.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 19.4 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 19.4.1 pci bus dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 19.4.2 serdes interface dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 19.5 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 19.5.1 serdes interface ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 19.5.2 pci bus 33-mhz ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 19.5.3 pci bus 66-mhz ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
june, 2006 contents pex 8111bb expresslane pci express-to-pci bridge data book xvii copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 20 physical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 20.1 pex 8111 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 20.2 mechanical drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 20.3 pcb layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 appendix a general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 a.1 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 a.2 united states and international representatives and distributors . . . . . . . . . . . . . . 264 a.3 technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
contents plx technology, inc. xviii pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book xix copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 registers 15-1. (offset 00h; pcivendid) pci vendor id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 15-2. (offset 02h; pcidevid) pci device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 15-3. (offset 04h; pcicmd ) pci command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 15-4. (offset 06h; pcistat) pci status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 15-5. (offset 08h; pcidevr ev) pci device revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-6. (offset 09h; pciclass) pci class code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-7. (offset 0ch; pcicachesize) pci cache line size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-8. (offset 0dh; pcilatency) pci bus lat ency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-9. (offset 0eh; pciheader) pci header ty pe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-10. (offset 0fh; pcibist) pci built-in self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15-11. (offset 10h; pcibase0) pci ba se address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15-12. (offset 14h; pcibase1) pci ba se address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15-13. (offset 18h; primbusnum) primary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15-14. (offset 19h; secbusnum) secondary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15-15. (offset 1ah; subbusnum) subordinate bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15-16. (offset 1bh; seclattimer) secondary latency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15-17. (offset 1ch; iobase) i/o base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 15-18. (offset 1dh; iolimit) i/o limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 15-19. (offset 1eh; secstat) secondary status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 15-20. (offset 20h; membase) memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 15-21. (offset 22h; memlimit) memory limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 15-22. (offset 24h; prebase) prefetchable memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 15-23. (offset 26h; prelimit) prefetchable memory limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 15-24. (offset 28h; prebaseupper) prefetchable memory base upper 32 bits . . . . . . . . . . . . . . . . . . . . . . .140 15-25. (offset 2ch; prelimitupper) prefetchab le memory limit upper 32 bits . . . . . . . . . . . . . . . . . . . . . . .140 15-26. (offset 30h; iobaseupper) i/o base upper 16 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 15-27. (offset 32h; iolimitupper) i/o limit upper 16 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 15-28. (offset 34h; pcicapptr) pci capabilities po inter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 15-29. (offset 3ch; pciintline) pci interrupt line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 15-30. (offset 3dh; pciintpin) pci interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 15-31. (offset 3eh; bridgectl) bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 15-32. (offset 40h; pwrmngid) power management capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 45 15-33. (offset 41h; pwrmngnext) power ma nagement next capability pointer . . . . . . . . . . . . . . . . . . . . . . .145 15-34. (offset 42h; pwrmngcap) power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 15-35. (offset 44h; pwrmngcsr) power management control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 15-36. (offset 46h; pwrmngbridge) power management bridge support . . . . . . . . . . . . . . . . . . . . . . . . . . .146 15-37. (offset 47h; pwrmngdata) power management data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15-38. (offset 48h; devspecctl) device-specifi c control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 15-39. (offset 50h; msiid) message signaled interrupts capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 15-40. (offset 51h; msinext) message signal ed interrupts next capability pointer . . . . . . . . . . . . . . . . . . . . .148 15-41. (offset 52h; msictl) message signaled interrupts control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 15-42. (offset 54h; msiaddr) message signaled interrupts address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15-43. (offset 58h; msiupperaddr) message signaled interrupts upper address . . . . . . . . . . . . . . . . . . . . .149 15-44. (offset 5ch; msidata) message signaled interrupts data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 15-45. (offset 60h; pciexid) pci express capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 15-46. (offset 61h; pciexnext) pci express next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 15-47. (offset 62h; pciexcap) pci express capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 15-48. (offset 64h; devcap) device capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 15-49. (offset 68h; devctl) pci express device control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 15-50. (offset 6ah; devstat) pci express device status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 15-51. (offset 6ch; linkcap) link capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 15-52. (offset 70h; linkctl) link control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 15-53. (offset 72h; linkstat) link status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 15-54. (offset 74h; slotcap) slot capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
registers plx technology, inc. xx pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15-55. (offset 78h; slotctl) slot control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 15-56. (offset 7ah; slotstat) slot status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 15-57. (offset 84h; mainindex) main control register index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15-58. (offset 88h; maindata) main control register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15-59. (offset 100h; pwrcaphdr) power budgeting capability header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15-60. (offset 104h; pwrdatasel) power budgeting data select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15-61. (offset 108h; pwrdata) power budgeting data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15-62. (offset 10ch; pwrbudcap) power budget capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15-63. (offset 110h; sercaphdr) serial number capability header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 15-64. (offset 114h; sernumlow) serial number low (lower dword) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15-65. (offset 118h; sernumhi) serial number hi (upper dword) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15-66. (offset 1000h; devinit) device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15-67. (offset 1004h; eectl) serial eeprom control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 15-68. (offset 1008h; eeclkfreq) serial eeprom clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15-69. (offset 100ch; pcictl) pci control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15-70. (offset 1010h; pcieirqenb) pci express interrupt request enable . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15-71. (offset 1018h; irqstat) interrupt request status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15-72. (offset 101ch; power) power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15-73. (offset 1020h; gpioctl) general-purpose i/o control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15-74. (offset 1024h; gpiostat) general-purpose i/o status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15-75. (offset 1030h; mailbox0) mailbox 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15-76. (offset 1034h; mailbox1) mailbox 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15-77. (offset 1038h; mailbox2) mailbox 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15-78. (offset 103ch; mailbox3) mailbox 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15-79. (offset 1040h; chiprev) chip silicon revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15-80. (offset 1044h; diagctl) diagn ostic control (factory test only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15-81. (offset 1048h; tlpcfg0) tlp controller configuration 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15-82. (offset 104ch; tlpcfg1) tlp controller configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15-83. (offset 1050h; tlpcfg2) tlp controller configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15-84. (offset 1054h; tlptag) tlp controller tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15-85. (offset 1058h; tlptimelimit0) tlp controller time limit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15-86. (offset 105ch; tlptimelimit1) tlp controller time limit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15-87. (offset 1060h; crstimer) crs timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15-88. (offset 1064h; ecfgaddr) enhanced configuration address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16-1. (offset 00h; pcivendid) pci vendor id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16-2. (offset 02h; pcidevid) pci device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 16-3. (offset 04h; pcicmd) pci command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 16-4. (offset 06h; pcistat) pci status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 16-5. (offset 08h; pcidevrev) pci de vice revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16-6. (offset 09h; pciclass) pci class code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16-7. (offset 0ch; pcicachesize) pci cache line size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16-8. (offset 0dh; pcilatency) pci bus latency timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16-9. (offset 0eh; pciheader) pci header type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16-10. (offset 0fh; pcibist) pci built-in self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16-11. (offset 10h; pc ibase0) pci base address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16-12. (offset 14h; pc ibase1) pci base address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16-13. (offset 18h; primbusnum) primary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16-14. (offset 19h; secbusnum) secondary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16-15. (offset 1ah; subbusnum) subordinate bus number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16-16. (offset 1ch; iobase) i/o base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16-17. (offset 1dh; iolimit) i/o limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16-18. (offset 1eh; secstat) secondary status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16-19. (offset 20h; membase) memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16-20. (offset 22h; memlimit) memory limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16-21. (offset 24h; pr ebase) prefetchable memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16-22. (offset 26h; prelimit) prefetchable memory limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16-23. (offset 28h; prebaseupper) prefetchable memory base upper 32 bits . . . . . . . . . . . . . . . . . . . . . . . 199 16-24. (offset 2ch; prelimitupper ) prefetchable memory limit upper 32 bits . . . . . . . . . . . . . . . . . . . . . . . 199 16-25. (offset 30h; iobaseupper) i/o base upper 16 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
june, 2006 registers pex 8111bb expresslane pci express-to-pci bridge data book xxi copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16-26. (offset 32h; iolimitupper) i/o limit upper 16 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 16-27. (offset 34h; pcicapptr) pci capabilities po inter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 16-28. (offset 3ch; pciintline) pci interrupt line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 16-29. (offset 3dh; pciintpin) pci interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 16-30. (offset 3eh; bridgectl) bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 16-31. (offset 40h; pwrmngid) power management capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 04 16-32. (offset 41h; pwrmngnext) power ma nagement next capability pointer . . . . . . . . . . . . . . . . . . . . . . .204 16-33. (offset 42h; pwrmngcap) power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 16-34. (offset 44h; pwrmngcsr) power management control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 16-35. (offset 46h; pwrmngbridge) power management bridge support . . . . . . . . . . . . . . . . . . . . . . . . . . .205 16-36. (offset 47h; pwrmngdata) power management data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16-37. (offset 48h; devspecctl) device-specifi c control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 16-38. (offset 50h; msiid) message signaled interrupts capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 16-39. (offset 51h; msinext) message signal ed interrupts next capability pointer . . . . . . . . . . . . . . . . . . . . .207 16-40. (offset 52h; msictl) message signaled interrupts control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 16-41. (offset 54h; msiaddr) message signaled interrupts address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16-42. (offset 58h; msiupperaddr) message signaled interrupts upper address . . . . . . . . . . . . . . . . . . . . .208 16-43. (offset 5ch; msidata) message signaled interrupts data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 16-44. (offset 60h; pciexid) pci express capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 16-45. (offset 61h; pciexnext) pci express next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 16-46. (offset 62h; pciexcap) pci express capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 16-47. (offset 64h; devcap) device capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 16-48. (offset 68h; devctl) pci express device control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 16-49. (offset 6ah; devstat) pci express device status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 16-50. (offset 6ch; linkcap) link capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 16-51. (offset 70h; linkctl) link control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 16-52. (offset 72h; linkstat) link status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 16-53. (offset 74h; slotcap) slot capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 16-54. (offset 78h; slotctl) slot control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 16-55. (offset 7ah; slotstat) slot status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 16-56. (offset 7ch; rootctl) root control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 16-57. (offset 80h; rootstat) root status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 16-58. (offset 84h; mainindex) main control register index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 16-59. (offset 88h; maindata) main control register data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 16-60. (offset 100h; pwrcaphdr) power budgeting capability header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 16-61. (offset 104h; pwrdatasel) power budgeting data select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16-62. (offset 108h; pwrdata) power budgeting data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 16-63. (offset 10ch; pwrbudcap) power budget c apability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 16-64. (offset 110h; sercaphdr) serial number capability header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4 16-65. (offset 114h; sernumlow) serial number low (lower dword) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 16-66. (offset 118h; sernumhi) serial number hi (upper dword) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 16-67. (offset 1000h; devinit) device initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 16-68. (offset 1004h; eectl) serial eeprom co ntrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 16-69. (offset 1008h; eeclkfreq) serial eeprom clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 16-70. (offset 100ch; pcictl) pci control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 16-71. (offset 1014h; pciirqenb) pci interrupt request enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 16-72. (offset 1018h; irqstat) interrupt request status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 16-73. (offset 1020h; gpioctl) general-purpose i/o control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 16-74. (offset 1024h; gpiostat) general-purpose i/o status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 16-75. (offset 1030h; mailbox0) mailbox 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 16-76. (offset 1034h; mailbox1) mailbox 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 16-77. (offset 1038h; mailbox2) mailbox 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 16-78. (offset 103ch; mailbox3) mailbox 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 16-79. (offset 1040h; chiprev) chip silicon revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 16-80. (offset 1044h; diagctl) diagnostic cont rol (factory test only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 16-81. (offset 1048h; tlpcfg0) tlp controller configuration 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 16-82. (offset 104ch; tlpcfg1) tlp controller configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 16-83. (offset 1050h; tlpcfg2) tlp controller configuration 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 16-84. (offset 1054h; tlptag) tlp controller tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
registers plx technology, inc. xxii pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16-85. (offset 1058h; tlptimelimit0) tlp controller time limit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16-86. (offset 105ch; tlptimelimit1) tlp controller time limit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16-87. (offset 1064h; ecfgaddr) enhanced configuration address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
pex 8111bb expresslane pci express-to-pci bridge data book 1 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 1 introduction 1.1 features forward and reverse transpar ent bridging between the pci express interface and pci bus pci express single-lane port (one virtual channel) pci express 2.5 gbps per direction pci express full split completion protocol 32-bit 66 mhz pci bus internal pci arbiter supporting up to 4 external pci masters spi serial eeprom port internal 8-kb shared ram available to the pci express interface and pci bus four gpio balls low-power cmos in 144-ball pbga or161-ball fbga package 1.5v pci express interface operating voltage, 3.3v i/o, 5v tolerant pci standards compliant ? pci local bus specification, revision 3.0 (pci r3.0) ? pci to pci bridge architecture specification, revision 1.1 (pci-to-pci bridge r1.1) ? pci bus power management interface specification, revision 1.1 (pci power mgmt. r1.1) ? pci express base specification, revision 1.0a (pci express r1.0a) ? pci express to pci/pci-x bridge specification, revision 1.0 (pci expressbridge r1.0) 1.2 overview the expresslane tm pex 8111 pci express-to-pci bridge allo ws for the use of ubiquitous pci silicon with the high-performance pci express network. as pci expre ss systems proliferate, there remain many applications that do not need the extensive bandwidth nor performance features of pci express. with the pex 8111, many existing chips and entire subsystems can be used, without modification, with pci express motherboards. 1.2.1 pci express endpoint interface full 2.5 gbps per direction single lane and single virtual channel operation compatible with multi-lane and multi-virtual channel pci express chips packetized serial traffic with pc i express split completion protocol data link layer crc generator and checker automatic retry of bad packets integrated low-voltage differential drivers 8b/10b signal encoding in-band interrupts and messages message signaled inte rrupt (msi) support
introduction plx technology, inc. 2 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 1.2.2 pci bus interface pci r3.0 -compliant 32-bit, 66 mhz pci interface pci master controller allows pci ex press access to pci target devices pci target controller ? allows full transparent acce ss to pci express resources ? allows memory-mapped access to shared ram and configuration registers pci arbiter supports up to four external pci bus masters power management registers and pci backplane pme# signal support message signaled interrupts (msi) support 1.2.3 configuration registers all internal registers are accessible from the pci express interface or pci bus all internal registers are set up through an external serial eeprom internal registers allow writes to and reads from an external serial eeprom internal registers allow control of gpio balls 1.2.4 data transfer pathways pci transparent bridge access to pci express pci memory-mapped single access to internal configuration registers pci memory-mapped single/burst access to internal shared ram indexed addressing capability registers (offsets 84h and 88h) pci configuration access to pci configurati on registers (reverse bridge mode only) pci express transparent bri dge access to pci bus targets pci express memory-mapped single access to internal configuration registers pci express memory-mapped single/bur st access to internal shared ram pci express configuration access to pci configur ation registers (forwa rd bridge mode only)
june, 2006 block diagrams pex 8111bb expresslane pci express-to-pci bridge data book 3 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 1.3 block diagrams figure 1-1. pex 8111 block diagram figure 1-2. pex 8111 typical forward bridge block diagram figure 1-3. pex 8111 typical reverse bridge block diagram configuration registers pci bus pci express interface fully transparent pci express to pci bridge pci interface pci express 8-kb shared memory pci express pex 8111 legacy pci chip proprietary pci asic pci bus serial eeprom pci-based cpu pci bus pex 8111 pci express i/o device pci express serial eeprom
introduction plx technology, inc. 4 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 5 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 2 ball descriptions 2.1 ball description abbreviations 2.2 pci signal pull-up resistors (forward bridge mode only) the pci balls discussed in this chapter are generic primary and secondary pci interface balls that do not have internal resistors. when designing motherboard s, system slot boards, ad apter boards, backplanes, and so forth, the termination of these balls must follow the guidelines detailed in the pci r3.0 . the following guidelines are not exhaustive and should be read in conjunction with the appropriate pci r3.0 sections. pci control signals require a pull-up resistor on the mo therboard, to ensure that these signals are always at valid values when a pci bus agent is not driving the bus. for a 32-bit pci bus, these control signals include the following: the int[d:a]# balls require pull-up resistors, regardless of whether they are used. depending on the application, m66en can also require a pull-up resist or. the value of these pull-up resistors depends on the bus loading. the pci r3.0 provides formulas for calculating the resistor values. when making adapter board devices where the pex 8111 port is wired to the pci connector, pull-up resistors are not required because they are pre-installed on the mo therboard. based on the ab ove, in an embedded design, pull-up resistors can be required for pci control signals on the bus. table 2-1. ball description abbreviations (pbga and fbga packages) abbreviation description # active low diff pci express differential buffer i input i/o bi-directional o output od open drain output pci pci-compatible buffer, 26-ma drive pd 50k-ohm pull-down resistor pu 50k-ohm pull-up resistor s schmitt trigger sts sustained three-state, driven high one clock cycle before float tp totem pole ts three-state devsel# int[d:a]# perr# stop# frame# irdy# serr# trdy#
ball descriptions plx technology, inc. 6 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.3 ball description ? 144-ball pbga package this section provides descriptions of the pex 8111 144-ball pbga package signal balls. the signals are divided into six groups: pci express signals pci signals clock, reset, and miscellaneous signals jtag interface signals test signals no connect signal power and ground signals 2.3.1 pci express signals table 2-2. pci express signals (9 balls) (144-ball pbga package) signal type balls description pern0 i diff b7 receive minus pci express differential receive signal. perp0 i diff a8 receive plus pci express differential receive signal. perst# i/o 6 ma 3.3v b12 pci express reset in forward bridge mode, perst# is an input. resets the entire pex 8111 when asserted. in reverse bridge mode, perst# is an output. asserted when a pci reset is detected. petn0 o diff a4 transmit minus pci express differential transmit signal. petp0 o diff b5 transmit plus pci express differential transmit signal. refclk- i diff b6 pci express clock input minus pci express differential, 100-mhz sp read spectrum re ference clock. connected to the pci express interface refclk- ball in forward bridge mode, and to an external differential clock driver in reverse bridge mode. refclk+ i diff a6 pci express clock input plus pci express differential, 100-mhz sp read spectrum re ference clock. connected to the pci express interfa ce refclk+ ball in forward bridge mode, and to an external differential clock driver in reverse bridge mode. wakein# i 3.3v c12 wake in signal in forward bridge mode, pull wakein# high. in reverse bridge mode, wakein# is an input, and indicates that the pci express device requested a wake up while the link remains in the l2 state. wakeout# od 6 ma 3.3v a9 wake out signal in forward bridge mode, wakeout# is an open drain output, which is asserted when pmein# is asserted and the link remains in the l2 state.
june, 2006 pci signals pex 8111bb expresslane pci express-to-pci bridge data book 7 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.3.2 pci signals table 2-3. pci signals (63 balls) (144-ball pbga package) signal type balls description ad[31:0] i/o ts pci j10, j12, j11, k12, l9, m9, k8, l8, k7, l7, m7, j6, k6, m6, l6, j5, h2, h1, g3, g2, g1, f4, f3, f2, e4, e3, e2, e1, d2, d1, c1, d3 address/data bus (32 balls) the pci address and data are multip lexed onto the same bus. during the address phase, ad[31:0] contain the ph ysical address of the transfer. during the data phase, ad[31:0] co ntain the data. ad31 is the most significant bit. write data is stable when irdy# is asserted, and read data is stable when trdy# is asserted. data is transferred when both irdy# and trdy# are asserted. cbe[3:0]# i/o ts pci m8, k5, h3, f1 command/byte enab le bus (4 balls) the bus command and byte enables ar e multiplexed onto the same bus. during the address phase, cbe[3:0]# contain the bus command. during the data phase, cbe[3:0]# contain th e byte enables. cbe0# corresponds to byte 0 (ad[7:0]), and cbe3# corresponds to byte 3 (ad[31:24]). cbe[3:0]# command 0000b interrupt acknowledge 0001b special cycle 0010b i/o read 0011b i/o write 0100b, 0101b reserved 0110b memory read 0111b memory write 1000b, 1001b reserved 1010b configuration read 1011b configuration write 1100b memory read multiple 1101b dual address cycle 1110b memory read line 1111b memory write and invalidate devsel# i/o sts pci pu (forward bridge mode only) k4 device select indicates that the target (bus slave) decoded its address during the current bus transaction. as an input, devs el# indicates whether a device on the bus was selected. frame# i/o sts pci pu (forward bridge mode only) m5 frame driven by the initiator. indicates access start and duration. when frame# is first asserted, the address phase is indicated. when frame# is de-asserted, the transaction remains in the last data phase. gnt[3:0]# i/o ts pci e11, f11, g9, g10 bus grant (4 balls) indicates that the central arbiter gran ted the bus to an agent. when the internal pci arbiter is en abled, gnt[3:0]# are outputs used to grant the bus to external devices. when the internal pci arbiter is disabled, gnt0# is an input used to grant the bus to the pex 8111. gnt[3:1]# are placed into high-impeda nce state.
ball descriptions plx technology, inc. 8 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 idsel i pci k9 initialization device select valid only in reverse bridge mode . used as a chip select during configuration read and write cycles. each pci slot or device typically contains an idsel connected to a signal address line, allowing the pci host to select individual sets of configuration registers. in forward bridge mode, it is recommended to ground idsel to prevent the signal from floating. inta#, intb#, intc#, intd# i/o od pci pu (forward bridge mode only) e12, e9, d11, e10 interrupt (4 balls) asserted to request an interrupt. after assertion, must re main asserted until the device driver clears it. int x # is level-sensitive and asynchronous to the clk. in forward bridge mode, int x # is an input from pci devices. all int x # signals are mapped into assert_int x and deassert_int x messages on the pci express interface. in reverse bridge mode, inti# is an output to the pci central resource function. all assert_int x and deassert_int x pci express messages are translated to int x # transitions on the pci bus. irdy# i/o sts pci pu (forward bridge mode only) l5 initiator ready indicates that the initiator (bus master) is ready to transfer data. data phase is complete when both irdy# and trdy# are asserted. lock# i/o sts pci m3 lock atomic operation indicates an atomic operation to a bridge that might require multiple transactions to complete. an output in forward bridge mode and an input in reverse bridge mode. m66en i pci d10 66 mhz enable indicates whether the pci bus is opera ting at 33 or 66 mhz. when low, and the pclko divider value in the device initialization register pclko clock frequency field is set to 011b, the pc lko ball oscillates at 33 mhz with a 50% duty cycle. when high, and the pclko divider value in the device initialization register pclko clock frequency field is set to 011b, the pclko ball oscillates at 66 mhz with a 33% duty cycle. read using the pci control register m66en bit. must be grounded in 33 mhz systems. par i/o ts pci j1 parity even parity is generated ac ross ad[31:0], and cbe[3:0]#. that is , the number of ones (1) on ad[31:0], cbe[3:0]#, and par is an even number. par is valid one clock after the addr ess phase. for data phases, par is valid one clock after irdy# is asserted on write cycles, and one clock after trdy# is asserted on read cycles. pa r has the same timing as ad[31:0], except it is delayed by one clock cy cle. the bus initiator drives par for address and write data phases, and the target drives par for read data phases. pcirst# i/o tp pci f10 pci reset in forward bridge mode, pcirst# is driven when a pci express reset is detected, or when the bridge control register secondary bus reset bit is set. in reverse bridge mode, pcirst# is an input that resets the entire pex 8111. reset is asserted and de -asserted asynchronously to clk, and is used to bring a pci device to an initial state. all pci signals are asynchronously placed into a hi gh-impedance stat e during reset. table 2-3. pci signals (63 balls) (144-ball pbga package) (cont.) signal type balls description
june, 2006 pci signals pex 8111bb expresslane pci express-to-pci bridge data book 9 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 pclki i pci d12 pci clock input all pci signals, except rst# and in terrupts, are sampled on the rising edge of pclki. the pclk1 frequency varies from 0 to 66 mhz, and it must oscillate during the serial eeprom initialization sequence. perr# i/o sts pci pu (forward bridge mode only) j3 parity error indicates that a data parity error occurred. driven active by the receiving agent two clocks following the da ta that contained bad parity. pmein# i s pci h12 power management event in valid only in forward bridge mode. input used to monitor requests to change the system?s power state. pmeout# od 24 ma 3.3v l12 power management event out valid only in reverse bridge mode. open drain output used to request a change in the power state. pmeout# is not 5v tolerant. when used in a system with a 5v pull-up resistor on the pci backplane pme# signal, an external voltage translation circuit is required. req[3:0]# i/o ts pci h11, g12, h9, g11 bus request (4 balls) indicates that an agent requires use of the bus. when the internal pci arbiter is enabled, req[3:0]# are i nputs used to service external bus requests. when the internal pci arbi ter is disabled, req0# is an output used to request bus control, and req[3:1]# are unused inputs. serr# i/o od pci pu (forward bridge mode only) j2 system error indicates that an address parity error, data parity error on the special cycle command, or other catastrophic error occurred. driven active for one pci clock period, and is synchronous to the clk. driven only in reverse bridge mode. stop# i/o sts pci pu (forward bridge mode only) l4 stop indicates that the target (bus slave) is requesting that the master stop the current transaction. after stop# is a sserted, stop# must remain asserted until frame# is de-asserted, wh ereupon stop# must be de-asserted. also, devsel# and trdy# cannot be changed until the current data phase completes. stop# must be de-a sserted in the clock following the completion of the last data phase, and must be placed into a high- impedance state in the next clock. data is transferred when both irdy# and trdy# are asserted, independent of stop#. trdy# i/o sts pci pu (forward bridge mode only) m4 target ready indicates that the target (bus slave) is ready to transfer data. data phase is complete when both irdy# and trdy# are asserted. table 2-3. pci signals (63 balls) (144-ball pbga package) (cont.) signal type balls description
ball descriptions plx technology, inc. 10 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.3.3 clock, reset, and miscellaneous signals table 2-4. clock, reset, and miscellaneous signals (13 balls) (144-ball pbga package) signal type balls description bar0enb# i 3.3v pu e8 pci base address 0 register enable when low, the pci base address 0 register is enabled. when high, the pci base address 0 register is enabled by the device-specific control register pci base address 0 enable bit. eeclk o 3 ma tp 3.3v b2 serial eeprom clock provides the clock to the serial eepr om. frequency is determined by the serial eeprom clock frequency register, and varies from 2 to 25 mhz. eecs# o 3 ma tp 3.3v c4 serial eeprom chip select active-low chip select. eerddata i 3.3v a1 serial eeprom read data used to read data from the pex 8111. a 47k-ohm pull-up resistor is required. eewrdata o 3 ma tp 3.3v a2 serial eeprom write data used to write data to the pex 8111. extarb i 3.3v k11 external arbiter enable when low, the internal pci arbiter services requests from an external pci device. when high, the pex 8111 requests the pci bus from an external arbiter. forward i 3.3v pu l11 bridge select when low, the pex 8111 acts as a pci-to-pci express bridge (reverse bridge). when high, the pex 8111 acts as a pci express-to-pci bridge (forward bridge). gpio[3:0] i/o 12 ma 3.3v pu a11, b10, a10, c9 general purpose i/o (4 balls) program as an input or output genera l-purpose ball. intern al device status is also an output on gpio[3:0]. interru pts are generated on balls that are programmed as inputs. the general-purpose i/o control register is used to configure these i/o. gpio0 defaults to a link status output. gpio1 defaults to an input. when gpio2 is low at the trailing edge of reset , the tlp controller configuration 0 register limit completion flow control credit bit is set. when gpio3 is low at the trailing edge of reset , the tlp controller configuration 0 register delay link training bit is set. for forward bridge mode, reset is perst#. for reverse bridge mode, reset is pcirst#.
june, 2006 jtag interface signals pex 8111bb expresslane pci express-to-pci bridge data book 11 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.3.4 jtag interface signals pclko o 26 ma tp pci h10 pci clock output buffered clock output derived from th e internal 100-mhz reference clock, with the frequency depending on the device initialization register pclko clock frequency field. signal frequency is 66 mhz when m66en is high. pclko is always driven and oscillates when one of the following occurs: pci express refclk-/+ input balls are active. pclko clock divider in device initialization register is non-zero. pclko can be connected to pclki as a source for the pci input clock. pwr_ok o 6 ma 3.3v b9 power ok valid only in forward bridge mode. when the available power indicated in the set slot power limit message is greater than or equal to the power requirement indicated in the power register, pwr_ok is asserted. table 2-5. jtag interface signals (5 balls) (144-ball pbga package) signal type balls description tck i m2 test clock joint test action group (jtag) test clock. sequences the tap controller as well as all pex 8111 jtag register s. ground when jtag is not used. tdi i pu l3 test data input serial data input to all jt ag instruction and data re gisters. the test access port (tap) controller state, as well as the particular instruction held in the instruction register determines which re gister is fed by tdi for a specific operation. tdi is sampled into the jtag registers on the rising edge of tck. hold open when jtag is not used. tdo o 12 ma 3.3v ts l1 test data output serial data output for all jtag inst ruction and data registers. the tap controller state, as well as the particular instruction held in the instruction register determines which register fe eds tdo for a specif ic operation. only one register (instruction or data) is a llowed as the active connection between tdi and tdo for any given operation. tdo changes state on the falling edge of tck and is only active dur ing the shifting of data through the pex 8111. placed into a hi gh-impedance st ate at all other times. hold open when jtag is not used. tms i pu m12 test mode select mode input signal to the tap controlle r. the tap controller is a 16-state fsm that provides the control logic for jtag. the tms state at the rising edge of tck determines the sequence of states for the tap controller. hold open when jtag is not used. trst# i pu l10 test reset resets the jtag tap controller when driven to ground. ground when jtag is not used. table 2-4. clock, reset, and miscellaneous signals (13 balls) (144-ball pbga package) (cont.) signal type balls description
ball descriptions plx technology, inc. 12 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.3.5 test signals 2.3.6 no connect signal caution: do not connect the following pex 8111 ball to board electrical paths, as this ball is not connected within the pex 8111. table 2-6. test signals (7 balls) (144-ball pbga package) signal type balls description bton i m11 test enable connect to ground for standard op operation. bunri i d8 test mode select connect to ground for standard operation. smc i k1 scan path mode control connect to ground for standard operation. test i a3 test mode select connect to ground for standard operation. tmc i c8 test mode control connect to ground for standard operation. tmc1 i b1 iddq test control input connect to ground for standard operation. tmc2 i m1 i/o buffer control connect to ground for standard operation. table 2-7. no connect signal ? 1 ball signal name type location description nc1 reserved c2 no connect must remain open. do not co nnect this ball to board electrical paths.
june, 2006 power and ground signals pex 8111bb expresslane pci express-to-pci bridge data book 13 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.3.7 power and ground signals table 2-8. power and ground signals (46 balls) (144-ball pbga package) signal type balls description avdd power e7 analog supply voltage connect to the +1.5v power supply. avss ground c7 analog ground connect to ground. gnd ground a12, b4, c3, c11, d9, e6, f12, g5, h4, h7, j4, j8, k2, k10 ground (14 balls) connect to ground. vdd_p power d5 pll supply voltage connect to the +1.5v filtered pll power supply. vdd_r power a7 receiver supply voltage connect to the +1.5v power supply. vdd_t power a5 transmitter supply voltage connect to the +1.5v power supply. vdd1.5 power c10, d4, f6, f8, g6, g7, j9, k3 pci express interface supply voltage (8 balls) connect to the +1.5v power supply. vdd3.3 power b3, b11, l2, m10 i/o supply voltage (4 balls) connect to the +3.3v power supply. vdd5 power f5, g8, h6 pci i/o clamp voltage (3 balls) connect to the +5.0v power supply for pci buffers. in a 3.3v pci environment, c onnect to the 3.3v power supply. vddq power e5, f9, g4, h5, h8, j7 i/o supply voltage (6 balls) connect to the +3.3v power supply for pci buffers. vss_c ground d7 common ground connect to ground. vss_p0 ground d6 pll ground connect to ground. vss_p1 ground c6 pll ground connect to ground. vss_r ground b8 receiver ground connect to ground. vss_re ground f7 receiver ground connect to ground. vss_t ground c5 transmitter ground connect to ground.
ball descriptions plx technology, inc. 14 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.3.8 ball tables ? 144-ball pbga package table 2-9. grid order (144-ball pbga package) grid signal grid signal grid signal grid signal a1 eerddata d1 ad2 g1 ad11 k1 smc a2 eewrdata d2 ad3 g2 ad12 k2 gnd a3 test d3 ad0 g3 ad13 k3 vdd1.5 a4 petn0 d4 vdd1.5 g4 vddq k4 devsel# a5 vdd_t d5 vdd_p g5 gnd k5 cbe2# a6 refclk+ d6 vss_p0 g6 vdd1.5 k6 ad19 a7 vdd_r d7 vss_c g7 k7 ad23 a8 perp0 d8 bunri g8 vdd5 k8 ad25 a9 wakeout# d9 gnd g9 gnt1# k9 idsel a10 gpio1 d10 m66en g10 gnt0# k10 gnd a11 gpio3 d11 intc# g11 req0# k11 extarb a12 gnd d12 pclki g12 req2# k12 ad28 b1 tmc1 e1 ad4 h1 ad14 l1 tdo b2 eeclk e2 ad5 h2 ad15 l2 vdd3.3 b3 vdd3.3 e3 ad6 h3 cbe1# l3 tdi b4 gnd e4 ad7 h4 gnd l4 stop# b5 petp0 e5 vddq h5 vddq l5 irdy# b6 refclk- e6 gnd h6 vdd5 l6 ad17 b7 pern0 e7 avdd h7 gnd l7 ad22 b8 vss_r e8 bar0enb# h8 vddq l8 ad24 b9 pwr_ok e9 intb# h9 req1# l9 ad27 b10 gpio2 e10 intd# h10 pclko l10 trst# b11 vdd3.3 e11 gnt3# h11 req3# l11 forward b12 perst# e12 inta# h12 pmein# l12 pmeout# c1 ad1 f1 cbe0# j1 par m1 tmc2 c2 nc1 f2 ad8 j2 serr# m2 tck c3 gnd f3 ad9 j3 perr# m3 lock# c4 eecs# f4 ad10 j4 gnd m4 trdy# c5 vss_t f5 vdd5 j5 ad16 m5 frame# c6 vss_p1 f6 vdd1.5 j6 ad20 m6 ad18 c7 avss f7 vss_re j7 vddq m7 ad21 c8 tmc f8 vdd1.5 j8 gnd m8 cbe3# c9 gpio0 f9 vddq j9 vdd1.5 m9 ad26 c10 vdd1.5 f10 pcirst# j10 ad31 m10 vdd3.3 c11 gnd f11 gnt2# j11 ad29 m11 bton c12 wakein# f12 gnd j12 ad30 m12 tms
june, 2006 ball tables ? 144-ball pbga package pex 8111bb expresslane pci express-to-pci bridge data book 15 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 table 2-10. signal order (144-ball pbga package) grid signal grid signal grid signal grid signal d3 ad0 f1 cbe0# e9 intb# m1 tmc2 c1 ad1 h3 cbe1# d11 intc# m12 tms d1 ad2 k5 cbe2# e10 intd# m4 trdy# d2 ad3 m8 cbe3# l5 irdy# l10 trst# e1 ad4 k4 devsel# m3 lock# d5 vdd_p e2 ad5 b2 eeclk c2 nc1 a7 vdd_r e3 ad6 c4 eecs# d10 m66en a5 vdd_t e4 ad7 a1 eerddata e8 bar0enb# c10 vdd1.5 f2 ad8 a2 eewrdata j1 par d4 f3 ad9 k11 extarb f10 pcirst# f6 f4 ad10 l11 forward d12 pclki f8 g1 ad11 m5 frame# h10 pclko g6 g2 ad12 a12 gnd b7 pern0 g7 g3 ad13 b4 a8 perp0 j9 h1 ad14 c3 j3 perr# k3 h2 ad15 c11 b12 perst# b3 vdd3.3 j5 ad16 d9 a4 petn0 b11 l6 ad17 e6 b5 petp0 l2 m6 ad18 f12 h12 pmein# m10 k6 ad19 g5 l12 pmeout# f5 vdd5 j6 ad20 h4 b9 pwr_ok g8 m7 ad21 h7 b6 refclk- h6 l7 ad22 j4 a6 refclk+ e5 vddq k7 ad23 j8 g11 req0# f9 l8 ad24 k2 h9 req1# g4 k8 ad25 k10 g12 req2# h5 m9 ad26 g10 gnt0# h11 req3# h8 l9 ad27 g9 gnt1# j2 serr# j7 k12 ad28 f11 gnt2# k1 smc d7 vss_c j11 ad29 e11 gnt3# l4 stop# d6 vss_p0 j12 ad30 c9 gpio0 m2 tck c6 vss_p1 j10 ad31 a10 gpio1 l3 tdi b8 vss_r e7 avdd b10 gpio2 l1 tdo f7 vss_re c7 avss a11 gpio3 a3 test c5 vss_t m11 bton k9 idsel c8 tmc c12 wakein# d8 bunri e12 inta# b1 tmc1 a9 wakeout#
ball descriptions plx technology, inc. 16 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.3.9 physical ball assignment ? 144-ball pbga package figure 2-1. 144-ball pbga physical ball assignment (underside view) mlk j hg f e dc ba tms pmeout# ad28 ad30 pmein# req2# gnd inta# pclki wakein# perst# gnd 12 bton forward extarb ad29 req3# req0# gnt2# gnt3# intc# gnd vdd3.3 gpio3 11 vdd3.3 trst# gnd ad31 pclko gnt0# pcirst# intd# m66en vdd1.5 gpio2 gpio1 10 ad26 ad27 idsel vdd1.5 req1# gnt1# vddq intb# gnd gpio0 pwr_ok wakeout# 9 cbe3# ad24 ad25 gnd vddq vdd5 vdd1.5 bar0enb# bunri tmc vss_r perp0 8 ad21 ad22 ad23 vddq gnd vdd1.5 vss_re avdd vss_c avss pern0 vdd_r 7 ad18 ad17 ad19 ad20 vdd5 vdd1.5 vdd1.5 gnd vss_p0 vss_p1 refclk- refclk+ 6 frame# irdy# cbe2# ad16 vddq gnd vdd5 vddq vdd_p vss_t petp0 vdd_t 5 trdy# stop# devsel# gnd gnd vddq ad10 ad7 vdd1.5 eecs# gnd petn0 4 lock# tdi vdd1.5 perr# cbe1# ad13 ad9 ad6 ad0 gnd vdd3.3 test 3 tck vdd3.3 gnd serr# ad15 ad12 ad8 ad5 ad3 nc1 eeclk eewrdata 2 tmc2 tdo smc par ad14 ad11 cbe0# ad4 ad2 ad1 tmc1 eerddata 1
june, 2006 ball description ? 161-ball fbga package pex 8111bb expresslane pci express-to-pci bridge data book 17 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.4 ball description ? 161-ball fbga package this section provides descriptions of the pex 8111 161-ball fbga package signal balls. the signals are divided into six groups: pci express signals pci signals clock, reset, and miscellaneous signals jtag interface signals test signals no connect signals power and ground signals 2.4.1 pci express signals table 2-11. pci express signals (9 balls) (161-ball fbga package) signal type balls description pern0 i diff b9 receive minus pci express differential receive signal. perp0 i diff a8 receive plus pci express differential receive signal. perst# i/o 6 ma 3.3v c12 pci express reset in forward bridge mode, perst# is an input. resets the entire pex 8111 when asserted. in reverse bridge m ode, perst# is an output. asserted when a pci reset is detected. petn0 o diff b5 transmit minus pci express differential transmit signal. petp0 o diff a6 transmit plus pci express differential transmit signal. refclk- i diff a7 pci express clock input minus pci express differential, 100-mhz spread spectrum reference clock. refclk- is connected to the pci e xpress interface re fclk- ball in forward bridge mode, and to an external differential clock driver in reverse bridge mode. refclk+ i diff b7 pci express clock input plus pci express differential, 100 mhz sp read spectrum re ference clock. refclk+ is connected to the pci express interface refclk+ ball in forward bridge mode, and to an external differential clock driver in reverse bridge mode. wakein# i 3.3v d14 wake in signal in forward bridge mode, pull wakein# high. in reverse bridge mode, wakein# is an input, and indicates that the pci express device requested a wakeup whil e the link remains in the l2 state. wakeout# od 6 ma 3.3v a11 wake out signal in forward bridge mode, wakeout# is an open drain output, and asserted when pmein# is asserted and the link remains in the l2 state.
ball descriptions plx technology, inc. 18 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.4.2 pci signals table 2-12. pci signals (63 balls) (161-ball fbga package) signal type balls description ad[31:0] i/o ts pci l13, j11, k12, l12, m10, p11, p10, p9, l9, n8, p8, m8, m7, l6, n6, p7, k2, j3, j1, h2, h3, h1, g4, f3, f2, f1, e2, e3, e1, d3, d1, d2 address/data bus (32 balls) the pci address and data are multipl exed onto the same bus. during the address phase, ad[31:0] contai n the physical address of the transfer. during the data phase, ad[31: 0] contain the data. ad31 is the most significant bi t. write data is stable when irdy# is asserted, and read data is stable when trdy# is asserted. data is transferred when both irdy# and trdy# are asserted. cbe[3:0]# i/o ts pci m9, p6, k1, g1 command/byte enable bus (4 balls) the bus command and byte enables are multiplexed onto the same bus. during the address phase, cbe[3 :0]# contain the bus command. during the data phase, cbe[3:0]# c ontain the byte enables. cbe0# corresponds to byte 0 (ad[7:0]), and cbe3# corresponds to byte 3 (ad[31:24]). cbe[3:0]# command 0000b interrupt acknowledge 0001b special cycle 0010b i/o read 0011b i/o write 0100b, 0101b reserved 0110b memory read 0111b memory write 1000b, 1001b reserved 1010b configuration read 1011b configuration write 1100b memory read multiple 1101b dual address cycle 1110b memory read line 1111b memory write and invalidate devsel# i/o sts pci pu (reverse bridge mode only) m4 device select indicates that the target (bus sl ave) decoded its address during the current bus transaction. as an input, devsel# indicates whether a device on the bus was selected. frame# i/o sts pci pu (reverse bridge mode only) l5 frame driven by the initiator, and indi cates the access start and duration. when frame# is first asserted, the address phase is indicated. when frame# is de-asserted, the transaction remains in the last data phase. gnt[3:0]# i/o ts pci f12, g11, j13, j14 bus grant (4 balls) indicates that the central arbiter granted the bus to an agent. when the internal pci arbiter is enabled, gnt[3:0]# are outputs used to grant the bus to external devices. when the internal pci arbiter is disabled, gnt0# is an input used to grant the bus to the pex 8111, and gnt[3:1]# are placed into a high-impedance state.
june, 2006 pci signals pex 8111bb expresslane pci express-to-pci bridge data book 19 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 idsel i pci n10 initialization device select valid only in reverse bridge mode . used as a chip select during configuration read and write cycles. each pci slot or device typically contains an idsel connected to a signal address line, allowing the pci host to select individual sets of configuration registers. in forward bridge mode, it is recommended to ground idsel to prevent the signal from floating. inta#, intb#, intc#, intd# i/o od pci pu (reverse bridge mode only) f14, f13, e14, e13 interrupt (4 balls) asserted to request an interrupt. afte r assertion, must remain asserted until the device driver clears it. int x # is level-sensitive and asynchronous to the clk. in forward bridge mode, int x # is an input from pci devices. all int x # signals are mapped into assert_int x and deassert_int x messages on the pci express interface. in reverse bridge mode, int x # is an output to the pci central resource function. all assert_int x and deassert_int x pci express messages are translated to int x # transitions on the pci bus. irdy# i/o sts pci pu (reverse bridge mode only) p5 initiator ready indicates that the initiator (bus master) is ready to transfer data. data phase is complete when both irdy# and trdy# are asserted. lock# i/o sts pci p4 lock atomic operation indicates an atomic operation to a bridge that might require multiple transactions to complete . output in forward bridge mode and input in reverse bridge mode. m66en i pci d13 66 mhz enable indicates whether the pci bus is operating at 33 or 66 mhz. when low, and the pclko divider value in the device initialization register pclko clock frequency field is set to 011b, the pclko ball oscillates at 33 mhz with a 50% duty cycle. when high, and the pclko divider value in the device initialization register pclko clock frequency field is set to 011b, the pclko ball oscillates at 66 mhz with a 33% du ty cycle. read m66en using the pci control register m66en bit. must be grounded in 33 mhz systems. par i/o ts pci j4 parity even parity is generated ac ross ad[31:0], and cbe[3:0]#. that is , the number of ones (1) on ad[31:0], cbe[3:0]#, and par is an even number. par is valid one clock af ter the address phase. for data phases, par is valid one clock after irdy# is asserted on write cycles, and one clock after trdy# is asse rted on read cycles. par has the same timing as ad[31:0], except it is delayed by one clock cycle. the bus initiator drives par for addre ss and write data phases, and the target drives par for read data phases. pcirst# i/o tp pci g14 pci reset in forward bridge mode, driven when a pci express reset is detected, or the bridge control register secondary bus reset bit is set. in reverse bridge mode, pcirst# is an input that resets the entire pex 8111. reset is asserted and de -asserted asynchronously to clk, and used to bring a pci device to an initial state. all pci signals are asynchronously placed into a hi gh-impedance state during reset. table 2-12. pci signals (63 balls) (161-ball fbga package) (cont.) signal type balls description
ball descriptions plx technology, inc. 20 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 pclki i pci e12 pci clock input all pci signals, except rst# and interrupts, are sampled on the rising edge of pclki. the pclk1 frequency varies from 0 to 66 mhz, and it must oscillate during the serial eeprom initialization sequence. perr# i/o sts pci pu (reverse bridge mode only) l2 parity error indicates that a data parity error occurred. driven active by the receiving agent two clocks following the data that contained bad parity. pmein# i s pci l14 power management event in valid only in forward bridge mode. input used to monitor requests to change the system power state. pmeout# od 24 ma 3.3v m14 power management event out valid only in reverse bridge mode. open-drain output used to request a change in the power state. pmeout# is not 5v tolerant. when used in a system with a 5v pull-up resistor on the pci backplane pme# signal, an external voltage translation circuit is required. req[3:0]# i/o ts pci h11, h12, k13, k14 bus request (4 balls) indicates that an agent requires use of the bus. when the internal pci arbiter is enabled, req[ 3:0]# are inputs used to service external bus requests. when the internal pci arbi ter is disabled, re q0# is an output used to request bus control, and req[3:1]# are unused inputs. serr# i/o od pci pu (reverse bridge mode only) l1 system error indicates that an address parity error, data parity error on the special cycle command, or other catastrophic error occurred. driven active for one pci clock period, and is synchronous to the clk. driven only in reverse bridge mode. stop# i/o sts pci pu (reverse bridge mode only) n4 stop indicates that the target (bus slave) is requesting that the master stop the current transaction. after stop# is asserted, it must remain asserted until frame# is de-asserted, wher eupon stop# must be de-asserted. also, devsel# and trdy# cannot be changed until the current data phase completes. stop# mu st be de-asserted in the clock following the completion of the last data phase, and must be placed into a high- impedance state in the ne xt clock. data is transferred when both irdy# and trdy# are asserted, independent of stop#. trdy# i/o sts pci pu (reverse bridge mode only) m5 target ready indicates that the target (bus slave) is ready to transfer data. data phase is complete when both irdy# and trdy# are asserted. table 2-12. pci signals (63 balls) (161-ball fbga package) (cont.) signal type balls description
june, 2006 clock, reset, and miscellaneous signals pex 8111bb expresslane pci express-to-pci bridge data book 21 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.4.3 clock, reset, and miscellaneous signals table 2-13. clock, reset, and miscellaneous signals (13 balls) (161-ball fbga package) signal type balls description bar0enb# i 3.3v pu a10 pci base address 0 register enable when low, the pci base address 0 register is enabled. when high, the pci base address 0 register is enabled by the device-specific control register pci base address 0 enable bit. eeclk o 3 ma tp 3.3v c2 serial eeprom clock provides the clock to the serial eepr om. frequency is determined by the serial eeprom clock frequency register, and varies from 2 to 25 mhz. eecs# o 3 ma tp 3.3v c5 serial eeprom chip select active-low chip select. eerddata i 3.3v b3 serial eeprom read data used to read data from the pe x 8111. a 47k-ohm pull-up resistor is required. eewrdata o 3 ma tp 3.3v a3 serial eeprom write data used to write data to the pex 8111. extarb i 3.3v m12 external arbiter enable when low, the internal pci arbiter services requests from an external pci device. when high, the pex 8111 requests the pci bus from an external arbiter. forward i 3.3v pu m13 bridge select when low, the pex 8111 acts as a pci-to-pci express bridge (reverse bridge). when high, the pex 8111 acts as a pci express-to-pci bridge (forward bridge).
ball descriptions plx technology, inc. 22 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 gpio[3:0] i/o 12 ma 3.3v pu b12, d11, a12, c10 general purpose i/o (4 balls) program as an input or output general-pur pose ball. internal de vice status also has the ability to be an output on gpio [3:0]. interrupts ar e generated on balls that are programmed as inputs. the general-purpose i/o control register is used to configure these i/o. gpio0 defaults to a link status output. gpio1 defaults to an input. when gpio2 is low at the trailing edge of reset , the tlp controller configuration 0 register limit completion flow control credit bit is set. when gpio3 is low at the trailing edge of reset , the tlp controller configuration 0 register delay link training bit is set. for forward bridge mode, reset is perst#. for reverse bridge mode, reset is pcirst#. pclko o 26 ma tp pci h14 pci clock output buffered clock output derived from th e internal 100-mhz reference clock, with the frequency depending on the device initialization register pclko clock frequency field. signal frequency is 66 mhz when m66en is high. pclko is always driven and oscillates when one of the following occurs: pci express refclk-/+ input balls are active, pclko clock divider in device initialization register is non-zero. pclko can be connected to pclki as a source for the pci input clock. pwr_ok o 6 ma 3.3v b11 power ok valid only in forward bridge mode. wh en the available power indicated in the set slot power limit message is greater than or equal to the power requirement indicated in the power register, pwr_ok is asserted. table 2-13. clock, reset, and miscellaneous signals (13 balls) (161-ball fbga package) (cont.) signal type balls description
june, 2006 jtag interface signals pex 8111bb expresslane pci express-to-pci bridge data book 23 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.4.4 jtag interface signals table 2-14. jtag interface signals (5 balls) (161-ball fbga package) signal type balls description tck i m2 test clock jtag test clock. sequences the ta p controller, as well as all pex 8111 jtag registers. ground when jtag is not used. tdi i pu p3 test data input serial data input to all jtag inst ruction and data registers. the tap controller state, as well as the particular instruction held in the instruction register determines which register is fed by tdi for a specific operation. tdi is sampled into the jtag registers on the rising edge of tck. hold open when jtag is not used. tdo o 12 ma ts 3.3v m3 test data output serial data output for all jtag inst ruction and data registers. the tap controller state, as well as the particular instruction held in the instruction register determines which register fe eds tdo for a specif ic operation. only one register (instruction or data) is allowed as the active connection between tdi and tdo for any given operation. tdo changes state on the falling edge of tck and is only active dur ing the shifting of data through the pex 8111. placed into a hi gh-impedance st ate at all other times. hold open when jtag is not used. tms i pu n12 test mode select mode input signal to the tap controlle r. the tap controller is a 16-state fsm that provides the control logic for jtag. the state of tms at the rising edge of tck determines the sequence of states for the tap controller. hold open when jtag is not used. trst# i pu n11 test reset resets the jtag tap controller when driven to ground. ground when jtag is not used.
ball descriptions plx technology, inc. 24 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.4.5 test signals 2.4.6 no connect signals caution: do not connect the following pex 8111 balls to board electrical paths, as these balls are not connected within the pex 8111. table 2-15. test signals (7 balls) (161-ball fbga package) signal type balls description bton i m11 test enable connect to ground for standard operation. bunri i c9 test mode select connect to ground for standard operation. smc i k3 scan path mode control connect to ground for standard operation. test i c4 test mode select connect to ground for standard operation. tmc i d10 test mode control connect to ground for standard operation. tmc1 i d4 iddq test control input connect to ground for standard operation. tmc2 i m1 i/o buffer control connect to ground for standard operation. table 2-16. no connect signals ? 18 balls signal name type location description nc reserved a1, a2, a13, a14, b1, b2, b13, b14, e5, n1, n2, n13, n14, p1, p2, p13, p14 no connect (17 balls) must remain open. do not co nnect these balls to board electrical paths. nc1 reserved c3 no connect must remain open. do not co nnect this ball to board electrical paths.
june, 2006 power and ground signals pex 8111bb expresslane pci express-to-pci bridge data book 25 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.4.7 power and ground signals table 2-17. power and ground signals (46 balls) (161-ball fbga package) signal type balls description avdd power c8 analog supply voltage connect to the +1.5v power supply. avss ground c6 analog ground connect to ground. gnd ground a4, c13, d5, d12, e4, e11, f11, j2, k4, k11, l4, m6, n9, p12 ground (14 balls) connect to ground. vdd_p power b6 pll supply voltage connect to the +1.5v filtered pll power supply. vdd_r power c7 receiver supply voltage connect to the +1.5v power supply. vdd_t power d6 transmitter supply voltage connect to the +1.5v power supply. vdd1.5 power b10, c1, c14, g2, g13, l3, l11, n7 pci express interface supply voltage (8 balls) connect to the +1.5v power supply. vdd3.3 power b4, c11, l10, n3 i/o supply voltage (4 balls) connect to the +3.3v power supply. vdd5 power g3, h13, l7 pci i/o clamp voltage connect to the +5.0v power supply for pci buffers. in a 3.3v pci environment, conne ct vdd5 to the 3.3v power supply. vddq power f4, g12, h4, j12, l8, n5 i/o supply voltage (6 balls) connect to the +3.3v power supply for pci buffers. vss_c ground d9 common ground connect to ground. vss_p0 ground d7 pll ground connect to ground. vss_p1 ground d8 pll ground connect to ground. vss_r ground a9 receiver ground connect to ground. vss_re ground b8 receiver ground connect to ground. vss_t ground a5 transmitter ground connect to ground.
ball descriptions plx technology, inc. 26 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.4.8 ball tables ? 161-ball fbga package table 2-18. grid order (161-ball fbga package) grid signal grid signal grid signal grid signal a1 nc c14 vdd1.5 h2 ad12 m5 trdy# a2 d1 ad1 h3 ad11 m6 gnd a3 eewrdata d2 ad0 h4 vddq m7 ad19 a4 gnd d3 ad2 h11 req3# m8 ad20 a5 vss_t d4 tmc1 h12 req2# m9 cbe3# a6 petp0 d5 gnd h13 vdd5 m10 ad27 a7 refclk- d6 vdd_t h14 pclko m11 bton a8 perp0 d7 vss_p0 j1 ad13 m12 extarb a9 vss_r d8 vss_p1 j2 gnd m13 forward a10 bar0enb# d9 vss_c j3 ad14 m14 pmeout# a11 wakeout# d10 tmc j4 par n1 nc a12 gpio1 d11 gpio2 j11 ad30 n2 a13 nc d12 gnd j12 vddq n3 vdd3.3 a14 d13 m66en j13 gnt1# n4 stop# b1 d14 wakein# j14 gnt0# n5 vddq b2 e1 ad3 k1 cbe1# n6 ad17 b3 eerddata e2 ad5 k2 ad15 n7 vdd1.5 b4 vdd3.3 e3 ad4 k3 smc n8 ad22 b5 petn0 e4 gnd k4 gnd n9 gnd b6 vdd_p e5 nc k11 n10 idsel b7 refclk+ e11 gnd k12 ad29 n11 trst# b8 vss_re e12 pclki k13 req1# n12 tms b9 pern0 e13 intd# k14 req0# n13 nc b10 vdd1.5 e14 intc# l1 serr# n14 b11 pwr_ok f1 ad6 l2 perr# p1 b12 gpio3 f2 ad7 l3 vdd1.5 p2 b13 nc f3 ad8 l4 gnd p3 tdi b14 f4 vddq l5 frame# p4 lock# c1 vdd1.5 f11 gnd l6 ad18 p5 irdy# c2 eeclk f12 gnt3# l7 vdd5 p6 cbe2# c3 nc1 f13 intb# l8 vddq p7 ad16 c4 test f14 inta# l9 ad23 p8 ad21 c5 eecs# g1 cbe0# l10 vdd3.3 p9 ad24 c6 avss g2 vdd1.5 l11 vdd1.5 p10 ad25 c7 vdd_r g3 vdd5 l12 ad28 p11 ad26 c8 avdd g4 ad9 l13 ad31 p12 gnd
june, 2006 ball tables ? 161-ball fbga package pex 8111bb expresslane pci express-to-pci bridge data book 27 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 c9 bunri g11 gnt2# l14 pmein# p13 nc c10 gpio0 g12 vddq m1 tmc2 p14 c11 vdd3.3 g13 vdd1.5 m2 tck c12 perst# g14 pcirst# m3 tdo c13 gnd h1 ad10 m4 devsel# table 2-19. signal order (161-ball fbga package) grid signal grid signal grid signal grid signal d2 ad0 c2 eeclk b1 nc m3 tdo d1 ad1 c5 eecs# b2 c4 test d3 ad2 b3 eerddata b13 d10 tmc e1 ad3 a3 eewrdata b14 d4 tmc1 e3 ad4 m12 extarb e5 m1 tmc2 e2 ad5 m13 forward n1 n12 tms f1 ad6 l5 frame# n2 m5 trdy# f2 ad7 a4 gnd n13 n11 trst# f3 ad8 c13 n14 b6 vdd_p g4 ad9 d5 p1 c7 vdd_r h1 ad10 d12 p2 d6 vdd_t h3 ad11 e4 p13 b10 vdd1.5 h2 ad12 e11 p14 c1 j1 ad13 f11 c3 nc1 c14 j3 ad14 j2 d13 m66en g2 k2 ad15 k4 a10 bar0enb# g13 p7 ad16 k11 j4 par l3 n6 ad17 l4 g14 pcirst# l11 l6 ad18 m6 e12 pclki n7 m7 ad19 n9 h14 pclko b4 vdd3.3 m8 ad20 p12 b9 pern0 c11 p8 ad21 j14 gnt0# a8 perp0 l10 n8 ad22 j13 gnt1# l2 perr# n3 l9 ad23 g11 gnt2# c12 perst# g3 vdd5 p9 ad24 f12 gnt3# b5 petn0 h13 p10 ad25 c10 gpio0 a6 petp0 l7 table 2-18. grid order (161-ball fbga package) (cont.) grid signal grid signal grid signal grid signal
ball descriptions plx technology, inc. 28 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 p11 ad26 a12 gpio1 l14 pmein# f4 vddq m10 ad27 d11 gpio2 m14 pmeout# g12 l12 ad28 b12 gpio3 b11 pwr_ok h4 k12 ad29 n10 idsel a7 refclk- j12 j11 ad30 f14 inta# b7 refclk+ l8 l13 ad31 f13 intb# k14 req0# n5 c8 avdd e14 intc# k13 req1# d9 vss_c c6 avss e13 intd# h12 req2# d7 vss_p0 m11 bton p5 irdy# h11 req3# d8 vss_p1 c9 bunri p4 lock# l1 serr# a9 vss_r g1 cbe0# a1 nc k3 smc b8 vss_re k1 cbe1# a2 n4 stop# a5 vss_t p6 cbe2# a13 m2 tck d14 wakein# m9 cbe3# a14 p3 tdi a11 wakeout# m4 devsel# table 2-19. signal order (161-ball fbga package) (cont.) grid signal grid signal grid signal grid signal
june, 2006 physical ball assignment ? 161-ball fbga package pex 8111bb expresslane pci express-to-pci bridge data book 29 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 2.4.9 physical ball assignment ? 161-ball fbga package figure 2-2. 161-ball fbga physical ball assignment (underside view) pnmlkjhgfedcba nc nc pmeout# pmein# req0# gnt0# pclko pcirst# inta# intc# wakein# vdd1.5 nc nc 14 nc nc forward ad31 req1# gnt1# vdd5 vdd1.5 intb# intd# m66en gnd nc nc 13 gnd tms extarb ad28 ad29 vddq req2# vddq gnt3# pclki gnd perst# gpio3 gpio1 12 ad26 trst# bton vdd1.5 gnd ad30 req3# gnt2# gnd gnd gpio2 vdd3.3 pwr_ok wakeout# 11 ad25 idsel ad27 vdd3.3 tmc gpio0 vdd1.5 bar0enb# 10 ad24 gnd cbe3# ad23 vss_c bunri pern0 vss_r 9 ad21 ad22 ad20 vddq vss_p1 avdd vss_re perp0 8 ad16 vdd1.5 ad19 vdd5 vss_p0 vdd_r refclk+ refclk- 7 cbe2# ad17 gnd ad18 vdd_t avss vdd_p petp0 6 irdy# vddq trdy# frame# nc gnd eecs# petn0 vss_t 5 lock# stop# devsel# gnd gnd par vddq ad9 vddq gnd tmc1 test vdd3.3 gnd 4 tdi vdd3.3 tdo vdd1.5 smc ad14 ad11 vdd5 ad8 ad4 ad2 nc1 eerddata eewrdata 3 nc nc tck perr# ad15 gnd ad12 vdd1.5 ad7 ad5 ad0 eeclk nc nc 2 nc nc tmc2 serr# cbe1# ad13 ad10 cbe0# ad6 ad3 ad1 vdd1.5 nc nc 1 bottom view (pex 8111)
ball descriptions plx technology, inc. 30 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 31 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 3 reset summary 3.1 forward bridge mode table 3-1 delineates which device resources are reset wh en each of the forwar d bridge reset sources are asserted. 3.2 reverse bridge mode table 3-2 delineates which device resources are reset wh en each of the reverse bridge reset sources are asserted. table 3-1. forward bridge reset reset sources device resources pci express interface logic pci interface logic pci rst# ball configuration registers pci express perst# ball ???? pci express link down ???? a a. general-purpose i/o control register is not reset for link down nor hot reset. pci express hot reset ???? a secondary bus reset bit ?? d3 to d0 power management reset ???? table 3-2. reverse bridge reset reset sources device resources pci express interface logic pci interface logic pci perst# ball pci express hot reset configuration registers pci rst# ball ????? secondary bus reset bit ?? d3 to d0 power management reset ?? ??
reset summary plx technology, inc. 32 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 3.3 initialization summary certain pex 8111 initialization sequences are described as follows: no serial eeprom, blank serial eeprom, or invalid serial eeprom ? when the eerddata ball is always high, th en an invalid serial eeprom is detected. in this case, the default pci device id (8111h) is selected. a 47k-ohm pull-up resistor ensures that eerddata is high when no serial eeprom is installed. ? enable the pci express an d pci interfaces, using default register values. valid serial eeprom with configuration register data ? enable the pci express and pci interfaces, using register values loaded from the serial eeprom. the device initialization register pci express enable or pci enable bit should be the last bit set by the serial eeprom.
pex 8111bb expresslane pci express-to-pci bridge data book 33 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 4 initialization 4.1 forward bridge initialization the actions that the pex 8111 takes upon receipt of certain reset timing and interface initialization requirements are described in the following sections. 4.1.1 forward bridge reset behavior there are three types of reset that the pex 8111 receives over the pci express primary interface: physical layer resets that are plat form specific and referred to as fundamental resets (cold/warm reset) pci express physical layer mechanism (hot reset) pci express data link transitioning to the down state of primary interface these three primary interface reset s ources are each described in the s ections that follow. all primary interface reset events initiate a seco ndary bus reset which resets the pc i bus. in addition to primary interface reset sources, the pex 8111 supp orts a pci bus reset by way of the bridge control register. after reset is de-asserted, a device attempting a configuration access to the pci bus behind the pex 8111 must wait for at least trhfa (2 25 ) pci clocks. 4.1.1.1 fundamental r eset (cold/warm reset) the pex 8111 uses the pci express perst# signal as a fundamental reset input. when perst# assertion follows the power-on event, it is referred to as a cold reset . the pci express system also generates this signal without removing power; which is referred to as a warm reset . the pex 8111 treats cold and warm resets without distinction. the pex 8111 state machines are asynchronously reset, and the configuration register s are initialized to their default values when perst# is asserted. the pex 8111 also places its pci outp uts into a high-impedance state, unl ess it is configured as the pci bus parking agent. the pex 8111 propagates the warm/cold reset from its primary interface to pci reset on the secondary interface. the pci rst# signal is assert ed while perst# is asserted. pcirst# is asserted for at least 2 ms after the power levels are valid. pci_rst# is asserted concurrent with perst# assertion. once asserted, however, pci_rst# remains asserted for 1.0 ms. if perst# de-asserts during th at time, pci_rst# remains active until 1.0 ms has elapsed from the time it asserted. if perst# is de-asserted after this time, pci_rst# follows the perst# de-assertion within two pci 33-mhz clock cycles (approximately 60 ns). 4.1.1.2 primary reset due to physi cal layer mechanism (hot reset) pci express supports the link training control reset (a training sequence with the hot reset bit set), or hot reset, for propagating reset requests down stream. when the pex 8111 receives a hot reset on its pci express primary interface, it propagates that reset to the pci rst# signal. in addition, the pex 8111 discards all transactions being processe d and returns all register s, state machines and externally observable state internal logic to the state-specified defau lt or initial conditions. software is responsible for ensuring that the li nk reset assertion and de-assertion messages are timed such that the pex 8111 adheres to proper reset assertion and de-assertion durations on the pci rst# signal.
initialization plx technology, inc. 34 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 4.1.1.3 primary reset due to data link down when the pex 8111 pci express primary interface re mains in standard oper ation and, for whatever reason, the link is down, the transaction and da ta link layers enter the dl_down state. the pex 8111 discards all transactions being processe d and returns all register s, state machines and externally observable state internal logic to the stat e-specified default or initial conditions. in addition, the entry of the primary interface of the pex 8111 into dl_down status initiates a reset of the pci bus, using the pci rst# signal. 4.1.1.4 secondary bus reset by wa y of bridge control register a pci secondary interface reset is initiated by setting the bridge control register secondary bus reset bit. this targeted reset is used for various r easons, including recovery from error conditions on the secondary bus, or to initiate re-enumeration. a write to the secondary bus reset bit forces the assertion of the secondary interface pci reset (rst#) signal without affecting the primary interface or configuration space registers. moreover, the logic associated with the secondary interface is re-initialized and transaction buffers associat ed with the secondary interface are cleared. rst# is asserted when the secondary bus reset bit is set; therefore, software must take care to observe proper pci reset timing requirements. software is responsible for ensuring that the pex 8111 does not receive transactions that require forw arding to the secondary interface while secondary bus reset bit is set. 4.1.1.5 bus parking during reset the pex 8111 drives the secondary interface pci bus ad[31:0], cbe[3:0]#, and par signals to a logic low level (zero) when the second ary interface rst# is asserted.
june, 2006 reverse bridge initialization pex 8111bb expresslane pci express-to-pci bridge data book 35 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 4.2 reverse bridge initialization 4.2.1 reverse bridge reset behavior a pci express hot reset (pci express link training sequence) is generated for the following cases: bridge control register secondary bus reset bit is set power management state transitions from d3 to d0 pci rst# assertion causes the pci express si deband reset signal (perst#) to assert. 4.2.2 reverse bridge secondary bus reset by way of bridge control register a pci express secondary interface reset is initiated by setting the bridge control register secondary bus reset bit. this targeted reset is used for various reasons, including recove ry from error conditions on the secondary bus, or to initiate re-enumeration. a write to the secondary bus reset bit causes a pci express link reset training sequence to transmit without affecting the primary inte rface or configuration space register s. moreover, the logic associated with the secondary interface is re -initialized and trans action buffers associated with the secondary interface are cleared.
initialization plx technology, inc. 36 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 37 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 5 interrupts 5.1 forward bridge pci interrupts in forward bridge mode, the pci int x # signals are inputs to the pex 8111. the interrupt is routed to the pci express interface , using virtual wire interrupt messages. the pci express interface supports the int x virtual wire interrupt feature for legacy systems that still support the pci int x # interrupt signals. pci int x # interrupts are ?virtualized? in the pci express interface, using assert_int x and deassert_int x messages, where x is a, b, c, or d for the respective pci int x # interrupt signals defined in the pci r3.0 . this message pairing provides a mechanism to preserve the level-sensitive semantics of the pci in terrupts. the assert_int x and deassert_int x messages transmitted on the pci express link capture the as serting/de-asserting edge of the respective pci int x # signal. the requester id used in the pci express assert_int x and deassert_int x messages transmitted by the pex 8111 (irrespective of whether the source is in ternal or external to the pex 8111) equals the pex 8111 primary inte rface bus and device numbers. the functio n number sub-field is cleared to 0. 5.1.1 forward bridge internally generated interrupts the following internal events can be programmed to generate an interrupt: serial eeprom transaction completed any gpio bit that is programmed as an input mailbox register written when one of these interrupts occurs, either a virt ual wire interrupt or message signaled interrupt is produced. both generated-interrupt methods are desc ribed, in detail, in the following two sections. the mailbox registers can be written in one of two ways from the downstream side: configuration transaction, using indexed addressing. the mailbox register can be accessed using the main control register index and main control register data registers to generate an interrupt. memory-mapped transaction, utilizing the address range defined by the pci base address 0 register.
interrupts plx technology, inc. 38 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 5.1.1.1 virtual wire interrupts when msi is disabled, virtual wire interrupts are used to support internal interrupt events. internal interrupt sources are masked by the pci command register interrupt disable bit and routed to one of the virtual interrupts using the pci interrupt pin register. pci express assert_int x and deassert_int x messages are not masked by the pci command register bus master enable bit. the internal interrupt is processed the same as the corresponding pci interrupt signal. 5.1.1.2 message signaled interrupts the pci express interface supports interrupts using message signaled interrupts (msi). with this mechanism, a device signals an in terrupt by writing to a specific memory location. the pex 8111 uses the 64-bit message address version of th e msi capability structure and clears the no snoop and relaxed ordering bits in the requester attributes. there ar e address and data co nfiguration registers associated with the msi feature ? message signaled interrupts address , message signaled interrupts upper address , and message signaled interrupts data . when an internal interrupt event occurs, the value in the message signaled interrupts data configuration register is written to the pci express address specified by the msi address configuration registers. the msi feature is enabled by the message signaled interrupts control register msi enable bit. when msi is enabled, th e virtual wire interrupt feature is disabled. msi interrupts are generated independently of the pci command register interrupt disable bit. msi interrupts are gated by the pci command register bus master enable bit. note: the no snoop and relaxed ordering bits are cleared because the pex 8111 does not support these features.
june, 2006 reverse bridge pci interrupts pex 8111bb expresslane pci express-to-pci bridge data book 39 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 5.2 reverse bridge pci interrupts in reverse bridge mode, the pci int x # signals are outputs from the pex 8111. each int x # signal is asserted or de-asserted when the corresponding pci express assert_int x or deassert_int x message is received. the int x # signals are asserted independently of the pci command register interrupt disable bit, and only when the pex 8111 remains in power state d0. 5.2.1 reverse bridge internally generated interrupts the following internal events can be programmed to generate an interrupt: serial eeprom transaction completed any gpio bit that is programmed as an input mailbox register written when one of these interrupt s occurs, either an int x # signal interrupt or message signaled interrupt is produced. both generated-interrupt methods are desc ribed, in detail, in the following two sections. the mailbox registers can be written in one of two ways from the downstream side: configuration transaction, using indexed addressing. the mailbox register can be accessed using the main control register index and main control register data registers to generate an interrupt. memory-mapped transaction, utilizing the address range defined by the pci base address 0 register. 5.2.1.1 int x # signals when an internal in terrupt event occurs, it causes a pci int x # signal to assert. internal interrupt sources are masked by the pci command register interrupt disable bit and are routed to one of the int x # signals, using the pci interrupt pin register. the int x # signals are asserted only when message signaled interrupts are disabled. 5.2.1.2 message signaled interrupts the pci bus supports interrupts using message si gnaled interrupts (msi). with this mechanism, a device signals an interrupt by writing to a speci fic memory location. the pex 8111 uses the 64-bit message address version of the ms i capability structure. there are address and data configuration registers associated with the msi feature ? message signaled interrupts address , message signaled interrupts upper address , and message signaled interrupts data . when an internal interrupt event occurs, the value in the message signaled interrupts data configuration register is written to the pci express address specified by the msi address configuration registers. the msi feature is enabled by the message signaled interrupts control register msi enable bit. when msi is enabled, the int x # interrupt signals for internally generated interrupts are disabled. msi interrupts are generated independently of the pci command register interrupt disable bit. msi interrupts are gated by the pci command register bus master enable bit.
interrupts plx technology, inc. 40 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 41 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 6 serial eeprom controller 6.1 overview the pex 8111 provides an interface to spi (seria l peripheral interface)-compatible serial eeproms. this interface consists of a chip se lect, clock, write data, and read data balls, and operates at up to 25 mhz. compatible 128-byte serial eeproms include the atmel at25010a, catalyst cat25c01, and st microelectronics m95010w. the pex 8111 su pports up to a 16 mb serial eeprom, utilizing 1-, 2-, or 3-byte addressing. the pex 8111 automati cally determines the appr opriate addressing mode. 6.2 serial eeprom data format the data in the serial eeprom is st ored in the format delineated in table 6-1 . table 6-1. serial eeprom data location value description 0h 5ah validation signature 1h refer to table 6-2 serial eeprom format byte 2h reg byte count (lsb) configurat ion register byte count (lsb) 3h reg byte count (msb) configurat ion register byte count (msb) 4h regaddr (lsb) 1 st configuration regi ster address (lsb) 5h regaddr (msb) 1 st configuration regi ster address (msb) 6h regdata (byte 0) 1 st configuration register data (byte 0) 7h regdata (byte 1) 1 st configuration register data (byte 1) 8h regdata (byte 2) 1 st configuration register data (byte 2) 9h regdata (byte 3) 1 st configuration register data (byte 3) ah regaddr (lsb) 2 nd configuration regi ster address (lsb) bh regaddr (msb) 2 nd configuration register address (msb) ch regdata (byte 0) 2 nd configuration register data (byte 0) dh regdata (byte 1) 2 nd configuration register data (byte 1) eh regdata (byte 2) 2 nd configuration register data (byte 2) fh regdata (byte 3) 2 nd configuration register data (byte 3) ?? reg byte count + 4 mem byte count (lsb) shared memory byte count (lsb) reg byte count + 5 mem byte count (msb) shared memory byte count (msb) reg byte count + 6 shared mem (byte 0) 1 st byte shared memory reg byte count + 7 shared mem (byte 1) 2 nd byte of shared memory ?? ffffh shared mem (byte n ) last byte of shared memory
serial eeprom controller plx technology, inc. 42 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 table 6-2 delineates the serial eepro m format byte organization. 6.3 initialization after the pex 8111 reset is de-asserted, the serial eepr om internal status regist er is read to determine whether a serial eeprom is installed. a pull-up re sistor on the eerddata ball produces a value of ffh when there is no serial eeprom installed. wh en a serial eeprom is detected, the first byte (validation signature) is read. when a value of 5ah is read, it is assumed that the serial eeprom is programmed for the pex 8111. the serial eeprom addr ess width is determined while this first byte is read. when the fi rst byte is not 5ah , then the serial eeprom is assumed to be blank or programmed with invalid data. in this case, the pci express and pci interfaces are enabled with device default settings. also, the serial eeprom control register serial eeprom address width field reports a value of 00b (undetermined width). when the serial eeprom contains valid data, the second byte (serial eeprom format byte) is read to determine which serial eeprom sections are loaded into the pex 8111 configuration registers and memory. bytes 2 and 3 determine the number of serial eeprom locations containing configuration register addresses and data. each configuration register entr y consists of two bytes of register address (bit 12 low selects the pci configuration registers; bit 12 high selects the memory-mapped configuration registers) and four bytes of register write data. wh en bit 1 of the serial eeprom format byte is set, locations reg byte count + 4 and reg byte count + 5 are read to determine the number of bytes to transfer from the serial eeprom into shared memory. the reg byte count must be a multiple of 6 and mem byte count must be a multiple of 4. the eeclk ball frequency is determined by the serial eeprom clock frequency register serial eeprom clock frequency field. the default clock frequency is 2 mhz. at this clock rate, it takes about 24 s per dword during configuration register or shared memory initialization. for faster loading of large serial eeproms that support a faster clock, direct the first configuration register load from the serial eeprom to the serial eeprom clock frequency register. this increases the serial eeprom clock frequency for subsequent dwords. note: when operating in forward bridge mode, it is recommended t that the serial eeprom sets the device initialization register pci express enable bit. when operating in reverse bridge mode, it is recommended that the serial eeprom sets the device initialization register pci enable bit. table 6-2. serial eeprom format byte bits description 0 configuration register load when cleared, and reg byte count is non-zero, the c onfiguration data is read from the serial eeprom and discarded. when set, configuration registers are loaded from th e serial eeprom. the firs t configuration register address is located at bytes 3 and 4 in the serial eeprom. 1 shared memory load when set, shared memory is lo aded from the serial eeprom, st arting at location reg byte count + 6. the byte number to load is determined by the value in serial eeprom locations reg byte count + 4 and reg byte count + 5. 7:2 reserved
june, 2006 serial eeprom random read/write access pex 8111bb expresslane pci express-to-pci bridge data book 43 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 6.4 serial eeprom random read/write access a pci express or pci bus master uses the serial eeprom control (eectl) register to access the serial eeprom. this register cont ains 8-bit read and write data fields, read and write start signals, and related status bits. the following ?c? routines demonstrate the firmwa re protocol required to access the serial eeprom through the serial eeprom control register. an interrupt is usually generated when the serial eeprom control register serial eeprom busy bit goes from true to false. 6.4.1 serial eeprom opcodes read_status_ee_opcode = 5 wren_ee_opcode = 6 write_ee_opcode = 2 read_ee_opcode = 3 6.4.2 serial eeprom low-level access routines int ee_waitidle() { int eectl, ii; for (ii = 0; ii < 100; ii++) { pex 8111read(eectl, eectl); = /* read current value in eectl */ if ((eectl & (1 << eeprom_busy)) == 0) = /* loop until idle */ return(eectl); } panic("eeprom busy timeout!\n"); } void ee_off() { ee_waitidle(); = /* make sure eeprom is idle */ pex 8111write(eectl, 0); = /* turn off everything (especially eeprom_cs_enable)*/ } int ee_readbyte() { int eectl = ee_waitidle(); = /* make sure eeprom is idle */ eectl |= (1 << eeprom_cs_enable) | (1 << eeprom_byte_read_start); pex 8111write(eectl, eectl); = /* start reading */ eectl = ee_waitidle(); = /* wait until read is done */ return((eectl >> eeprom_read_data) & 0xff); = /* extract read data from eectl */ } void ee_writebyte(int val) { int eectl = ee_waitidle(); = /* make sure eeprom is idle */ eectl &= ~(0xff << eeprom_write_data); = /* clear current write value */ eectl |= (1 << eeprom_cs_enable) | (1 << eeprom_byte_write_start) | ((val & 0xff) << eeprom_write_data); pex 8111write(eectl, eectl); } 6.4.3 serial eeprom read status routine ... ee_writebyte(read_status_ee_opcode); = /* read status opcode */ status = ee_readbyte(); = /* get eeprom status */ ee_off(); = /* turn off eeprom */ ...
serial eeprom controller plx technology, inc. 44 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 6.4.4 serial eeprom write data routine ... ee_writebyte(wren_ee_opcode); = /* must first write-enable */ ee_off(); = /* turn off eeprom */ ee_writebyte(write_ee_opcode); = /* opcode to write bytes */ #ifdef three_byte_address_eeprom = /* three-byte addressing eeprom? */ ee_writebyte(addr >> 16); = /* transmit high byte of address */ #endif ee_writebyte(addr >> 8); = /* transmit next byte of address */ ee_writebyte(addr); = /* transmit low byte of address */ for (ii = 0; ii < n; ii++) { ee_writebyte(buffer[ii]); = /* transmit data to be written */ } ee_off(); = /* turn off eeprom */ ... 6.4.5 serial eeprom read data routine ... ee_writebyte(read_ee_opcode); = /* opcode to write bytes */ #ifdef three_byte_address_eeprom = /* three-byte addressing eeprom? */ ee_writebyte(addr >> 16); = /* transmit high byte of address */ #endif ee_writebyte(addr >> 8); = /* transmit next byte of address */ ee_writebyte(addr); = /* transmit low byte of address */ for (ii = 0; ii < n; ii++) { buffer[ii] = ee_readbyte(buffer[ii]); /* store read data in buffer */ } ee_off(); = /* turn off eeprom */
pex 8111bb expresslane pci express-to-pci bridge data book 45 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 7 address spaces 7.1 introduction the pex 8111 supports the following address spaces: pci-compatible configuratio n (00h to ffh; 256 bytes) pci express extended configuration (100h to fffh) i/o (32-bit) memory (32-bit non-prefetchable) prefetchable me mory (64-bit) the first two spaces are used for accessing configuration regi sters. (refer to chapter 8, ?configuration transactions,? for details.) pci express extended configuration space (100h to f ffh) is supported only in forward bridge mode. table 7-1 lists which bus is primary or secondary for the pex 8111 forward and reverse bridge modes. the other three address spaces determine which tr ansactions are forwarded from the primary to secondary bus, and from the secondary to primary bu s. the memory and i/o ranges are defined by a set of base and limit registers in the configuration header. tran sactions falling within the ranges defined by the base and limit registers are forwarded from the primary to secondary bus. transactions falling outside these ranges are forwarded from the secondary to primary bus. the pex 8111 does not perform address translation (flat address space) when transactions cross the bridge. table 7-1. primary and secondary bus definitions for forward and reverse bridge modes bridge mode primary bus secondary bus forward bridge pci express pci reverse bridge pci pci express
address spaces plx technology, inc. 46 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 7.2 i/o space the i/o address space determines whether to forwar d i/o read or i/o write transactions across the pex 8111. pci express uses the 32-bit short addres s format (dword-aligned) for i/o transactions. 7.2.1 enable bits the pex 8111?s response to i/o transactions is controlled by five configuration register bits: pci command register i/o access enable bit pci command register bus master enable bit bridge control register isa enable bit bridge control register vga enable bit bridge control register vga 16-bit decode bit the i/o access enable bit must be set for i/o transactions to be forwarded downstream. when cleared: all i/o transactions on the secondary bus are forwarded to the primary bus forward bridge mode ? all pr imary interface i/o requests are completed with unsupported request status reverse bridge mode ? all i/o transactions ar e ignored (no devsel# assertion) on the primary (pci) bus the bus master enable bit must be set for i/o transactions to be forwarded upstream. when cleared: forward bridge mode ? all i/o transactio ns on the secondary (pci) bus are ignored reverse bridge mode ? all i/o requests on the s econdary (pci express) bus are completed with unsupported request status the isa enable bit is discussed in section 7.2.3, ?isa mode.? the vga enable and vga 16-bit decode bits are discussed in section 7.2.4, ?vga mode.? 7.2.2 i/o base and limit registers the following i/o base and limit configuration registers are used to determine whether to forward i/o transactions acr oss the pex 8111: i/o base (upper four bits of 8-bit register correspond to addr ess bits [15:12]) i/o base upper 16 bits (16-bit register correspond s to address bits [31:16]) i/o limit (upper four bits of 8-bit register correspond to address bits [15:12]) i/o limit upper 16 bits (16-bit register correspond to address bits [31:16]) the i/o base consists of one 8-bit register and one 16-bit register. the upper four bits of the 8-bit i/o base register define bits [15:12] of the i/o base a ddress. the lower four b its of the 8-bit register determine the i/o address capability of this device. the 16 bits of the i/o base upper 16 bits register define bits [31:16] of the i/o base address. the i/o limit consists of one 8-bit register and one 16-bit register. the upper four bits of the 8-bit i/o limit register define bits [15:12] of the i/o limit ad dress. the lower four bits of the 8-bit register determine the i/o address capability of this device, and reflect the value of the same field in the i/o base register. the 16 bits of the i/o limit upper 16 bits register define bits [31:16] of the i/o limit address.
june, 2006 i/o base and limit registers pex 8111bb expresslane pci express-to-pci bridge data book 47 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 because address bits [11:0] are no t included in the address space decoding, the i/o address range has a granularity of 4 kb and is always aligned to a 4-kb address boundary space. the maximum i/o range is 4 gb. i/o transactions on the primary bus that fall within the range defined by the i/o base and limit registers are forwarded downstream to the secondary bus, and i/o transactions on the secondary bus that are within the range are ignored. i/o transactions on the prim ary bus that do not fall within the range defined by the i/o base and limit registers are ignored, and i/o trans actions on the secondary bus that do not fall within the range are forwarded upstream to the primary bus. figure 7-1 illustrates i/o forwarding. for 16-bit i/o addressing, when the i/o base has a value greater than the i/o limit , the i/o range is disabled. for 32-bit i/o addressing, wh en the i/o base specified by the i/o base and i/o base upper 16 bits registers has a value greater than the i/o limit specified by the i/o limit and i/o base upper 16 bits registers, the i/o range is disabled. in these cases, all i/o transactions are forwarded upstream, and no i/o transactions are forwarded downstream. figure 7-1. i/o forwarding i/o base i/o limit 4 kb multiple primary bus secondary bus i/o address space downstream upstream
address spaces plx technology, inc. 48 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 7.2.3 isa mode the bridge control register isa enable bit supports i/o forwarding in a system that contains an isa bus. the isa enable bit only affects i/o addresses that are within the range defined by the i/o base and limit registers, and are in the firs t 64 kb of the i/o address space. when the isa enable bit is set, the pex 8111 does not forward downstream i/o transactions on the primary bus that are in the top 768 bytes of each 1- kb block within the first 64 kb of address space. only transactions in the bottom 256 bytes of each 1-kb block are forwarded downstream. when the isa enable bit is clear, all addresses within the range defined by the i/o base and limit registers are forwarded downstream. i/o transactions with addr esses above 64 kb are forwarded according to the range defined by the i/o base and limit registers. when the isa enable bit is set, the pex 8111 forwards upstream i/o transactions on the secondary bus that are in the top 768 bytes of each 1-kb block w ithin the first 64 kb of ad dress space, although the address is within the i/o base and limit. all othe r transactions on the secondary bus are forwarded upstream when they fall outside the range defined by the i/o base and limit registers. when the isa enable bit is clear, all secondary bus i/o addresses outside the range defined by the i/o base and limit registers are forwarded upstream. as with all upstream i/o transactions, the pci command register bus master enable bit must be set to enable upstream forwarding. figure 7-2 illustrates i/o forwarding with the isa enable bit set. figure 7-2. i/o forwarding with the isa enable bit set secondary bus 000h - 0ffh primary bus 400h - 4ffh 800h - 8ffh 900h - bffh 500h - 7ffh 100h - 3ffh downstream upstream
june, 2006 vga mode pex 8111bb expresslane pci express-to-pci bridge data book 49 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 7.2.4 vga mode the bridge control register vga enable bit enables vga register accesses to be forwarded downstream from the primary to s econdary bus, independent of the i/o base and limit registers. the bridge control register vga 16-bit decode bit selects between 10- and 16-bit vga i/o address decoding, and is applicable when the vga enable bit is set. the vga enable and vga 16-bit decode bits control the following vga i/o addresses: 10-bit addressing ? address bits [9:0] = 3b0h through 3bbh, and 3c0h through 3dfh 16-bit addressing ? address bits [15:0] = 3b0h through 3bbh, and 3c0h through 3dfh these ranges apply only to the fi rst 64 kb of i/o address space. 7.2.4.1 vga palette snooping separate vga palette snooping is not supported by pci express-to-pci bridges; however, the pex 8111 supports palette snooping in reverse bridge mode. in forward bridge mode, the bridge control register vga enable bit determines whether vga palette accesses are forwarded from pci express-to-pci. the pci command register vga palette snoop bit is forced to 0 in forward bridge mode. the bridge control register vga 16-bit decode bit selects between 10- and 16-bit vga i/o palette snooping address decoding, and is applicable when the vga palette snoop bit is set. the vga palette snoop and vga 16-bit decode bits control the following vga i/o palette snoop addresses: 10-bit addressing ? address bits [9:0] = 3c6h, 3c8h, and 3c9h 16-bit addressing ? address bits [15:0] = 3c6h, 3c8h, and 3c9h the pex 8111 supports the following three modes of palette snooping: ignore vga palette accesses when there are no graphi cs agents downstream th at need to snoop or respond to vga palette access cycles (reads or writes) positively decode and forward vga palette writes when there are graphics agents downstream of the pex 8111 that require to snoop palette writes (reads are ignored) positively decode and forward vga palette read s and writes when ther e are graphics agents downstream that require to snoop or respond to vga palette access cycles (reads or writes) the bridge control register vga enable bit and pci command register vga palette snoop bit select the pex 8111?s response to palette accesses, as delineated in table 7-2 . note: x is ?don?t care.? table 7-2. pex 8111 response to palette access vga enable vga palette snoop pex 8111 response to palette accesses 0 0 ignore all palette accesses 0 1 positively decode palette writes (ignore reads) 1 x positively decode palette reads and writes
address spaces plx technology, inc. 50 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 7.3 memory-mapped i/o space the memory-mapped i/o address space determines whether to forward n on-prefetchable memory read or write transactions across the pex 8111. ma p devices that experience side effects during reads, such as buffers, into this space. for pci-to-pci expr ess reads, prefetching o ccurs in this space only when the memory read line or me mory read multiple commands ar e issued on the pci bus. for pci express-to-pci reads, the byte number to read is determined by the memory read request tlp. transactions that are forwar ded using this address space are limited to a 32-bit range. 7.3.1 enable bits the pex 8111?s response to memory-mapped i/o tran sactions is controlled by three configuration register bits: pci command register memory space enable bit pci command register bus master enable bit bridge control register vga enable bit the memory space enable bit must be set for memory transactions to be forwarded downstream. when cleared: all memory transactions on the secondary bus are forwarded to the primary bus forward bridge mode ? all non-posted memory requests are completed with an unsupported request status, and posted write data is discarded reverse bridge mode ? all memory transac tions are ignored on the primary (pci) bus the bus master enable bit must be set for memory tran sactions to be forwarded upstream. when cleared: forward bridge mode ? all memory transact ions on the secondary (pci) bus are ignored reverse bridge mode ? all non-posted memory re quests on the secondary (pci express) bus are completed with an unsupported request status, and posted write data is discarded the vga enable bit is discussed in section 7.3.3, ?vga mode.? 7.3.2 memory base and limit registers the following memory base and limit configuration registers are used to determine whether to forward memory-mapped i/o tran sactions across the pex 8111: memory base (bits [15:4] of 16-bit register correspond to address bits [31:20]) memory limit (bits [15:4] of 16-bit register correspond to address bits [31:20]) bits [15:4] of the memory base register define bits [31:20] of the memory-mapped i/o base address. bits [15:4] of the memory limit register define bits [31:20] of the memory-mapped i/o limit address. bits [3:0] of each register are hardwired to 0h. because address bits [19:0] are not included in the address space decoding, the memory-mapped i/o address range has a granularity of 1 mb and is always aligned to a 1-mb address boundary space. the maximum memory-mapped i/o range is 4 gb. memory transactions that fall within the range defined by the memory base and limit registers are forwarded downstream from the pr imary to secondary bus, and memory transactions on the secondary bus that are within th e range are ignored.
june, 2006 vga mode pex 8111bb expresslane pci express-to-pci bridge data book 51 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 memory transactions that do not fall within the range defined by the memory base and limit registers are ignored on the primary bus, and forwarded upstr eam from the secondary bu s (provided they are not in the address range defined by the set of prefetchable memory address registers or forwarded downstream by the vga mechanism). figure 7-3 illustrates memory-mapped i/o forwarding. when the memory base is programmed to have a value greater than the memory limit , then the memory-mapped i/o range is disabled. in this case, all memory transaction forwarding is determined by the prefetchable base and limit registers and the bridge control register vga enable bit. figure 7-3. memory-mapped i/o forwarding 7.3.3 vga mode the bridge control register vga enable bit enables vga frame buffer accesses to be forwarded downstream from the primary to s econdary bus, independent of the memory base and limit registers. the vga enable bit controls vga memory addresses 0a0000h through 0bffffh. memory base memory limit 1 mb multiple primary bus secondary bus memory-mapped i/o address space downstream upstream
address spaces plx technology, inc. 52 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 7.4 prefetchable space the prefetchable address space dete rmines whether to forward prefet chable memory read or write transactions across the pex 8111. map devices that do not experience side effects during reads into this space. for pci-to-pci express reads, prefetching occurs in this sp ace for all memory read commands (memory read, memory read line, and memo ry read multiple) issued on the pci bus for memory read commands, the device-specific control register blind prefetch enable bit must be set for prefetching to occur for pci express-to-pci reads, the byte number to read is determined by the memory read request; therefore, pref etching does not occur 7.4.1 enable bits the pex 8111?s response to prefet chable address space is controlled by three configuration register bits: pci command register memory space enable bit pci command register bus master enable bit bridge control register vga enable bit for further details, refer to section 7.3.1, ?enable bits.? 7.4.2 prefetchable base and limit registers the following prefetchable memory base and limit configuration registers are used to determine whether to forward prefetchable memo ry transactions across the pex 8111: prefetchable memory base (bits [15:4] of 16-bit register correspond to address bits [31:20]) prefetchable memory base upper 32 bits (32-bit register corresponds to address bits [63:32]) prefetchable memory limit (bits [15:4] of 16-bit register correspond to address bits [31:20]) prefetchable memory limit upper 32 bits (32-bit register corresponds to address bits [63:32]) bits [15:4] of the prefetchable memory base register define bits [31:20 ] of the prefetchable memory base address. bits [15:4] of the prefetchable memory limit register define bits [31:20] of the prefetchable memory limit. for 64-bit addressing, the prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits registers are also used to define the space. because address bits [19:0] are not included in the address space d ecoding, the prefetchable memory address range has a granularity of 1 mb and is always aligned to a 1-mb address boundary space. the maximum prefetchable me mory range is 4 gb with 32-bit addressing, and 2 61 bytes with 64-bit addressing. memory transactions that fall within the range defined by the prefetchable memory base and limit registers are forwarded downstream from the primary to secondary bus, and memory transactions on the secondary bus that are within the range are ignored. memory transactions that do not fall within the range defined by the prefetchable memory base and limit registers are ignored on the primary bus, an d forwarded upstream from the secondary bus (provided they are not in the address range defined by the set of memory-mapped i/o address registers or forwarded downstream by the vga mechanism).
june, 2006 prefetchable base and limit registers pex 8111bb expresslane pci express-to-pci bridge data book 53 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 when the prefetchable memory base is programmed to a value greater than the prefetchable memory limit , then the prefetchable memory range is disa bled. in this case, a ll memory transaction forwarding is determined by the memory base and limit registers and the bridge control register vga enable bit. consider the four prefetchable memory base and limit registers when disabling the prefetchable range. figure 7-4 illustrates both memory-mapped i/o and prefetchable memory forwarding. in the illustration, dual addr ess cycles (dac) indicate 64-bit addressing. figure 7-4. memory-mapped i/o and prefetchable memory forwarding prefetchable memory base prefetchable memory limit primary bus secondary bus prefetchable and memory-mapped i/o memory space memory-mapped i/o limit memory-mapped i/o base 4-gb boundary dac dac dac dac sac sac sac sac sac sac sac sac sac = single address cycle dac = dual address cycle 1 mb multiple 1 mb multiple downstream upstream
address spaces plx technology, inc. 54 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 7.4.3 64-bit addressing unlike memory-mapped i/o memory that must be below the 4-gb address boundary space, prefetchable memory is located below, above, or span the 4-gb address boundary space. memory locations above the 4-gb address boundary space must be accessed using 64-bit addressing. pci express memory transactions that use the short address (32-bit) fo rmat target the non-prefetchable memory space, or a prefetchable memory windo w below the 4-gb address boundary space. pci express memory transactions that us e the long address (64-bit) format target locations anywhere in the 64-bit memory space. pci memory transactions that use single address cycles only target locations below the 4-gb address boundary space. pci memory transac tions that use dual address cycl es target locations anywhere in the 64-bit memory space. the first address phase of dual address transactions contains the lower 32 bits of the address, and the second address phase c ontains the upper 32 bits of the address. when the upper 32 bits of the address are zero (0h), a si ngle address transaction is always performed. 7.4.3.1 forward bridge mode below 4-gb address boundary space if the prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits registers are both cleared to 0, addresses above the 4-gb address boundary space are not supported . in forward bridge mode, if a pci express memory tran saction is detected with an address above 4 gb, the transaction is completed with unsupported reques t status. all dual address transactions on the pci bus are forwarded upstream to the pci express interface. above 4-gb address boundary space if the prefetchable memory is located entir ely above the 4-gb address boundary space, the prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits registers are both set to non-zero values. if a pci express memory transaction is detected with an address below 4 gb, the transaction is completed with unsupported request status, and all single address transactions on the pci bus are forwarded upstream to the pci expr ess interface (unless the transactions fall within the memory-mapped i/o or vga memory range). a pci express memory transaction above the 4-gb address boundary space, that falls within the range defined by the prefetchable memory base , prefetchable memory base upper 32 bits , prefetchable memory limit , and prefetchable memory limit upper 32 bits registers, is forwarded downstream a nd becomes a dual address cycle on the pci bus. if a dual address cycle is detected on the pci bus that is outside the range defined by these registers, it is forwarded upstre am to the pci express interface. if a pci express memory transaction above the 4-gb address boundary space does not fall within the range defined by these registers, it is completed with unsupported request status. if a pci dual address cycle falls within the range determined by these registers, it is ignored.
june, 2006 64-bit addressing pex 8111bb expresslane pci express-to-pci bridge data book 55 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 spans 4-gb address boundary space if the prefetchable memory spans the 4-gb address boundary space, the prefetchable memory base upper 32 bits register is cleared to 0, and the prefetchable memory limit upper 32 bits register is set to a non-zero value. if a pci express memory transaction is det ected with an address below the 4-gb address boundary space, and is greater than or equal to the prefetchable memory base address, then the transaction is forwarded downstream. a single address transac tion on the pci bus is forwarded upstream to the pci express interface, if the address is less than the prefetchable memory base address. if a pci express memory transacti on above the 4-gb address boundary space is less than or equal to the prefetchable memory limit register, it is forwarded downstream to the pci bus as a dual address cycle. if a dual address cycle on the pci bus is less than or equal to the prefetchable memory limit register, it is ignored. if a pci express memory transaction above the 4-gb address boundary space is greater than the prefetchable memory limit register, it is completed with unsupported request status. if a dual address cycle on the pci bus is greater than the prefetchable memory limit register, it is forwarded upstream to the pci express interface.
address spaces plx technology, inc. 56 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 7.4.3.2 reverse bridge mode below 4-gb address boundary space if the prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits registers are both cleared to 0, then addr esses above the 4-gb address boundary space are not supported . in reverse bridge mode, if a dual address transaction on the pci bus is detected, the transaction is ignored. if a pci express memory tran saction is detected with an address above the 4-gb address boundary space, it is forwarded upstream to the pci bus as a dual address cycle. above 4-gb address boundary space if the prefetchable memory is located entir ely above the 4-gb address boundary space, the prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits registers are both set to non-zero values. the pex 8111 ignores all single address memory transactions on the pci bus, and forwards all pci express memory tran sactions with addresses below the 4-gb address boundary space upstream to the pci bus (unless th ey fall within the memory-mapped i/o or vga memory range). a dual address transaction on the pci bus th at falls within the range defined by the prefetchable memory base , prefetchable memory base upper 32 bits , prefetchable memory limit , and prefetchable memory limit upper 32 bits registers is forwarded downstream to the pci express interface. if a pci express memory transaction is above the 4-gb addres s boundary space and falls outside the range defined by these registers, it is fo rwarded upstream to the pc i bus as a dual address cycle. dual address transactions on the pci bus that do not fall within the range defined by these registers are ignored. if a pci express memory transaction above the 4-gb address boundary space falls within the range defined by these registers, it is completed with unsupported request status. spans 4-gb address boundary space if the prefetchable memory spans the 4-gb address boundary space, the prefetchable memory base upper 32 bits is cleared to 0, and the prefetchable memory limit upper 32 bits register is set to a non-zero value. if a pci single addre ss cycle is greater than or equal to the prefetchable memory base address, then the transaction is forwarded downstr eam to the pci express interface. if a pci express memory transaction is detected wi th an address below the 4-gb ad dress boundary space, and is less than the prefetchable memory base address, then the transaction is forwarded upstream to the pci bus. if a dual address pci transaction is less than or equal to the prefetchable memory limit register, it is forwarded downstream to the pci express interface. if a pci express memory transaction above the 4-gb address boundary space is less than or equal to the prefetchable memory limit register, it is completed with unsupported request status. if a du al address pci transaction is greater than the prefetchable memory limit register, it is ignored. if a pci ex press memory transaction above the 4-gb address boundary space is greater than the prefetchable memory limit register, it is forwarded upstream to the pci bus as a dual address cycle. when a pci express memory transactio n above 4 gb is greater than the prefetchable memory limit register, it is forwarded upstream to the pci bus as a dual address cycle. 7.4.4 vga mode the bridge control register vga enable bit enables vga frame buffer accesses to be forwarded downstream from the primary to secondary bus, independent of the prefetchable memory base and prefetchable memory limit registers. the vga enable bit controls vga memory addresses 0a0000h through 0bffffh.
pex 8111bb expresslane pci express-to-pci bridge data book 57 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 8 configuration transactions 8.1 introduction configuration requests are initiated only by the root complex in a pci express-based system, or by the central resource function in a pci-based system. in the pci r3.0 , the term central resource is used to describe bus support functions supplied by the host system, typically in a pci-compliant bridge or standard chipset. (refer to the pci r3.0 , section 2.4, for further details.) devices in a pci express or pci system have a c onfiguration space that is accessed using type 0 or type 1 configuration transactions: type 0 configuration transacti ons are used to access internal pex 8111 configuration registers type 1 configuration transactions are used to access pex 8111 devices that reside downstream the configuration address is formatted as follows. table 8-1. pci express 31 24 23 19 18 16 15 12 11 8 72 10 bus number device number function number rsvd extended register address register address rsvd table 8-2. pci type 0 (at initiator) 31 16 15 11 10 8 72 10 single bit decoding of device number rsvd function number register number 00 table 8-3. pci type 0 (at target) 31 11 10 8 72 10 rsvd function number register number 00 table 8-4. pci type 1 31 24 23 16 15 11 10 8 72 10 rsvd bus number device number function number register number 01
configuration transactions plx technology, inc. 58 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8.2 type 0 configuration transactions the pex 8111 only responds to type 0 configuration transactions on its primary bus that address the pex 8111 configuration space. a type 0 configuratio n transaction is used to configure the pex 8111, and is not forwarded downstream to the secondar y bus. the pex 8111 ignores type 0 configuration transactions on the secondary bus. type 0 configurat ion transactions always result in the transfer of 1dword. when configuration write data is poisoned, the da ta is discarded, and a non-fatal error message is generated, when enabled. 8.3 type 1 configuration transactions type 1 configuration transactions are used for device configuration in a hierarchical bus system. the pex 8111 responds to type 1 configuration transact ions. type 1 configuration transactions are used when the transaction is intended for a device resi ding on a bus other than the one where the type 1 request is issued. the bus number field in a configuration tr ansaction request specifies a unique bus in the hierarchy on which transaction targets reside. the pex 8111 compares the specified bus number with two pex 8111 configuration registers ? secondary bus number and subordinate bus number ? to determine whether to forward a type 1 configuration transaction across the pex 8111. when a type 1 configuration tran saction is received on the primary interface, the following tests are applied, in sequence, to the bus number field to determine how the transaction must be handled: if the bus number field is equal to the secondary bus number register value, and the conditions for converting the trans action into a special cycle transactio n are met, the pex 8111 forwards the configuration request to the secondary bus as a special cycle transaction. when the conditions are not met, the pex 8111 forwards the configurat ion request to the secondary bus as a type 0 configuration transaction. if the bus number field is not equal to the secondary bus number register value, but is within the range of the secondary bus number and subordinate bus number (inclusive) registers, the type 1 configuration request is specifying a bu s located behind the pe x 8111. in this case, the pex 8111 forwards the configuration request to the secondary bus as a type 1 configuration transaction. if the bus number field does not satisfy the above criteria, the type 1 configuration request is specifying a bus that is not located behind the pex 8111. in this case, the configuration request is invalid: ? if the primary interface is pci express, a completion with unsupp orted request status is returned ? if the primary interface is pci, the config uration request is ignored, resulting in a master abort
june, 2006 type 1-to-type 0 conversion pex 8111bb expresslane pci express-to-pci bridge data book 59 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8.4 type 1-to-type 0 conversion the pex 8111 performs a type 1-to-type 0 conversion when the type 1 transaction is generated on the primary bus and is intended for a device directly attached to the secondary bus. the pex 8111 must convert the type 1 configuration transaction to type 0, thereby allowing the pex 8111 to respond to it. type 1-to-type 0 conversions are performed only in the downstream direction. the pex 8111 generates type 0 configuration transactions only on the s econdary interface, never on the primary interface. 8.4.1 forward bridge mode the pex 8111 forwards a type 1 transaction on the pc i express interface to a type 0 transaction on the pci bus, when the following are true: type 1 configuration request bus number field is equal to the secondary bus number register value. conditions for conversion to a speci al cycle transaction are not met. the pex 8111 then performs the fo llowing on the s econdary interface: 1. clears address bits ad[1:0] to 00b. 2. derives address bits ad[7:2] from the configuration request register address field. 3. derives address bits ad[10:8] from the configuration request function number field. 4. clears address bits ad[15:11] to 0h. 5. decodes the device number field and asserts a single address bit in the range ad[31:16] during the address phase. 6. verifies that the configuration request extended register address field is zero (0h). when the value is non-zero, the pex 8111 does not forward the transaction, and treats it as an unsupported request on the pci express interface, and a received master abort on the pci bus. type 1-to-type 0 transactions are pe rformed as non-posted transactions.
configuration transactions plx technology, inc. 60 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8.4.2 reverse bridge mode the pex 8111 forwards a type 1 transaction on the pci bus to a type 0 transaction on the pci express interface, when the following are true during the pci address phase: address bits ad[1:0] are 01b. type 1 configuration request bus number field (ad[23:16]) is equal to the secondary bus number register value. bus command on cbe[3:0]# is a configuration read or write. type 1 configuration request device number field (ad[15:11]) is zer o (0h). when the value is non-zero, the transaction is ignore d, resulting in a master abort. the pex 8111 then creates a pci express conf iguration request, according to the following: 1. sets the request type field to configuration type 0. 2. sets the register address field [7:2] from the configuration request register address field. 3. clears the extended register address field [11:8] to 0h. 4. sets the function number field [18:16] from the configuration request function number field. 5. clears the device number field [23:19] from the configuration request device number field (forced to 0h). 6. sets the bus number field [31:24] from the configuration request bus number field. type 1-to-type 0 transactions are performe d as non-posted (del ayed) transactions.
june, 2006 type 1-to-type 1 forwarding pex 8111bb expresslane pci express-to-pci bridge data book 61 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8.5 type 1-to-type 1 forwarding type 1-to-type 1 transaction forwarding provides a hierarchical configuratio n mechanism when two or more levels of bridges are used. when the pex 8111 detects a type 1 configuration transaction intended for a pci bus downstream from the secondary bus, it forwards the transaction unchanged to the secondary bus. in this case, the transac tion target does not reside on the pe x 8111 secondary interface; however, is located on a bus segment further downstream. ultimate ly, this transaction is converted to a type 0 or special cycle transaction by a downstream bridge. 8.5.1 forward bridge mode the pex 8111 forwards a type 1 transaction on the pc i express interface to a type 1 transaction on the pci bus when the following are true: type 1 configuration transaction is detected on the pci express. value specified by the bus number field is within the range of bus numbers between the secondary bus number (exclusive) and subordinate bus number (inclusive). the pex 8111 then performs the fo llowing on the s econdary interface: 1. generates address bits ad[1:0] as 01b. 2. generates the pci register number, function number, device number, and bus number from the pci express configuration request register address , function number , device number , and bus number fields, respectively. 3. generates address bits ad[31:24] as 0h. 4. verifies that the configuration request extended register address field is 0h. when the value is non-zero, the pex 8111 does not forward the transaction, and returns a completion with unsupported request status on the pci express in terface, and a received master abort on the pci bus. type 1-to-type 1 forwarding transactions are performed as non- posted transactions.
configuration transactions plx technology, inc. 62 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8.5.2 reverse bridge mode the pex 8111 forwards a type 1 transaction on the pci bus to a type 1 transaction on the pci express interface when the following are true during the pci address phase: address bits ad[1:0] are 01b. value specified by the bus number field is within the range of bus numbers between the secondary bus number (exclusive) and subordinate bus number (inclusive). bus command on cbe[3:0]# is a configuration read or write. the pex 8111 then creates a pci express conf iguration request, according to the following: 1. sets the configuration request type field to configuration type 1. 2. sets the register address field [7:2] from the configuration request register address field. 3. clears the extended register address field [11:8] to 0h. 4. sets the function number field [18:16] from the configuration request function number field. 5. sets the device number field [23:19] from the configuration request device number field. 6. sets the bus number field [31:24] from the configuration request bus number field. type 1-to-type 1 forwarding transactions are pe rformed as non-posted (delayed) transactions. 8.6 type 1-to-special cycle forwarding the type 1 configuration mechanism is used to ge nerate special cycle transactions in hierarchical systems. special cycle transactions are ignored by the pex 8111 acting as a target, and are not forwarded across the pex 8111. in forward bridge mode, special cy cle transactions are only genera ted in the downstream direction (pci express-to-pci). in reverse bridge mode, special cycle transactions are also generated in the downstream direction (pci-to-pci express). a type 1 configuration write requ est on the pci express interface is converted to a special cycle on the pci bus when the following conditions are met: type 1 configuration request bus number field is equal to the secondary bus number register value. device number field is all ones (1h) function number field is all ones (1h) register address field is all zeros (0h) extended register address field is all zeros (0h) when the pex 8111 initiates the transaction on the pci bus, the bus command is converted from a configuration write to a sp ecial cycle. the address and data fiel ds are forwarded, unchanged, from the pci express-to-pci bus. target devices that reco gnize the special cycle ignore the address, and the message is passed in the data word. the transaction is performed as a non-posted transaction; however, the pci target response (always master abort in this case) is not returned to pci express. after the master abort is detected on the pci bus, the succes sful completion tlp is returned to pci express.
june, 2006 pci express enhanced configuration mechanisms pex 8111bb expresslane pci express-to-pci bridge data book 63 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8.7 pci express enhanced configuration mechanisms the pci express enhanced configuration m echanism adds four extra bits to the register address field, to expand the space to 4,096 bytes. the pex 8111 forwards configuration transactions only when the extended register address bits are all zeros (0h). this prevents addres s aliasing on the pci bus, which does not support extended register addressing. when a configuration transactio n targets the pci bus and contains a non-zero value in the extended register address bits, the pex 8111 treats the transaction as if it received a master abort on the pci bus. the pex 8111 performs the following: 1. sets the appropriate status bits for the destinat ion bus, as if the tran saction had executed and received a master abort. 2. generates a pci express completion with unsupported request status. 3. indexed addressing of the main control block registers. 8.7.1 memory-mapped indirect (reverse bridge mode only) in reverse bridge mode, the pex 8111 provides th e capability for a pci hos t to access the downstream pci express configuration registers, using pci memory transactions. the 4-kb region of the memory range defined by the pci base address 0 register is used for this m echanism. memory reads and writes to pci base address 0 register offsets 2000h to 2fffh re sult in a pci express configuration transaction. the transaction a ddress is determined by the enhanced configuration address register. the format of this address register is delineated in table 8-5 . after the enhanced configuration address register is programmed to point to a particular device, the entire pci express endpoint 4-kb configuration space is directly accessed, using memory read and write transactions. only single dwords are transf erred during enhanced configuration transactions. table 8-5. enhanced configuration address register format 31 30 28 27 20 19 15 14 12 11 0 enhanced enable rsvd bus number device number function number rsvd
configuration transactions plx technology, inc. 64 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8.8 configuration retry mechanism 8.8.1 forward bridge mode bridges are required to return a completion for al l configuration requests that cross the pex 8111 from pci express-to-pci, prior to expiration of the root complex?s completion timeout timer. this requires that bridges take ownership of all co nfiguration requests forwarded across the pex 8111. when the configuration request to pci successfu lly completes prior to the pex 8111?s crs timer ( crs timer register, offset 1060h) expiration, the pex 8111 returns a completion with successful status to pci express. when the configuration request to pci encounters an error condition prior to the crs timer expiration, the pex 8111 returns an appropriate error completion to pci express. when the configuration request to pci does not co mplete successfully or with an error, prior to crs timer expiration, then the pex 8111 returns a completion with configuration retry status (crs) to pci express. although the pex 8111 returned a completion with crs to pci express, the pex 8111 continues to keep the configuration trans action alive on the pci bus. the pci r3.0 states that after a pci master detects a target retry, it must continue to retry th e transaction until at least one dword is transferred. the pex 8111 retries the transaction until it completes on the pci bus, or until the pci express-to-pci retry timer expires. when another pci express-to-pci configuration tr ansaction is detected wh ile the previous one is retried, a completion with crs is immediately returned. if the first configuration transaction completes on the pci bus after the second configuration transaction returns with a comple tion of crs status on the pc i express interf ace, the pex 8111 discards the completion information. bridges that implement this option are also required to implement bit 15 of the pci express device control register as the bridge configuration retry enable bit. when the bridge configuration retry enable bit is cleared, the pex 8111 does not return a completion with crs on behalf of configuration requests forwarded across the pex 8111. the lack of a completion results in eventual completion timeout at the root complex. by default, bridges do not return crs for configuration requests to a pci device behind the pex 8111, which might result in lengthy completion delays that must be comprehended by the completion timeout value in the root complex. 8.8.2 reverse bridge mode in reverse bridge mode, the pex 8111 detects completion with crs status from a downstream pci express device. the device-specific control register crs retry control field determines the pex 8111 response in reverse bridge mode when a pci-to-pci express configuration transaction is terminated with a configuration request retry status. table 8-6. crs retry control crs retry control response 00b retry one time after one sec ond. when another crs is received, target abort on the pci bus. 01b retry eight times, one time pe r second. when another crs is received, target abort on the pci bus. 10b retry one time pe r second, until successful completion. 11b reserved
pex 8111bb expresslane pci express-to-pci bridge data book 65 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 9 bridge operation 9.1 forward bridge operation in forward bridge mode, the pex 8111 presents a type 1 configuration space header (bridge) on the pci express interface. there are no pci-compatible confi guration registers avai lable on the pci bus. three sets of type 1 configuration space header re gisters define the bridgi ng operation between the pci express interface and pci bus. (refer to table 9-1 .) the pex 8111 also supports one pci base address re gister (bar), which allows a pci express or pci master to access internal configur ation registers or shared memory . during bus enumeration, the addresses corresponding to the bar are excluded from the bridging ranges of the six registers referenced in table 9-1 . table 9-1. type 1 configuration space header register sets that define bridging operation between pci express interface and pci bus register set description i/o base and i/o limit when i/o transactions on the pci express in terface fall within the range specified by these registers, the transactions are forwarded to the pci bus. when i/o transactions on the pci bus fall outside the range specified by these registers, the transactions are forwarded to the pci express interface. memory base and memory limit when non-prefetchable memory transactions on the pci express interface fall within the range specified by these regist ers, the transactions are forwarded to the pci bus. when non-prefetchable me mory transactions on the pci bus fall outside the range specified by these regi sters, the transactions are forwarded to the pci express interface. prefetchable memory base and prefetchable memory limit when prefetchable memory transacti ons on the pci express interface fall within the range specified by these registers, the transactions are forwarded to the pci bus. when prefetchable memo ry transactions on the pci bus fall outside the range specified by these regist ers, the transactions are forwarded to the pci express interface.
bridge operation plx technology, inc. 66 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.1 forward bridge flow control the pex 8111 supports the flow control mechanism described in the pci express base 1.0a , and provides the minimum flow requirements delineated in table 9-2 . the pex 8111 advertises infinite credits (initial credit value of 0h) for completion header and completion data. buffer space is al located for the resulti ng completions. th e unit of flow control (fc) for data is 16 bytes. for headers, it is the maximum size header plus tlp digest. 9.1.2 forward bridge buffer size and management the pex 8111 provides adequate buffers to accept data transfers from the pci express interface, and to deliver a read completion. for upstream requests (pci-to-pci express), the pe x 8111 provides buffer space for the resultant completion (data and/or header) before the trans action is forwarded to the pci express interface. 9.1.3 forward bridge requester id and tag assignment in certain cases, the pex 8111 must generate a new requester id and tag combination for transactions forwarded to the pci express interface. when the pex 8111 generates a new requester id for a transaction forwarded from the secondary interface to the primary interface, the pex 8111 assigns the pci express requester id, using the secondary in terface?s bus number, and clears the device number and function number fields to 0. the requester id is a 16-bit field formatted as follows, and the tag is a unique 8-bit field. outstanding non-posted transactions ( such as transactions requiring a completion) forwarded to the pci express interface must have a unique transaction id, regardless of whether multiple pci express transactions were generated for a single pci transaction. when a pci non-posted transaction forwarded to the pci express interface crosses a 4-kb addr ess boundary space, or a read request exceeds the pci express device control register maximum read request size field value, the resulting multiple pci express transactions require unique transaction ids. table 9-2. flow control mechanism minimum flow requirements credit type minimum advertisement ph (posted request headers) 8 fc unit ? credit value of 08h pd (posted request data payload) 64 fc unit ? credit value of 40h nph (non-posted request header) 8 fc unit ? credit value of 08h npd (non-posted request data payload) 8 fc unit ? credit value of 08h cplh (completion headers) infi nite ? credit value of 00h cpld (completion data payload) infinite ? credit value of 00h 15 87 32 0 bus number device number function number
june, 2006 forward bridge pci express-to-pci forwarding (downstream) pex 8111bb expresslane pci express-to-pci bridge data book 67 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.4 forward bridge pci express- to-pci forwarding (downstream) 9.1.4.1 transaction types table 9-3 delineates the pci express transactions th at must be forwarded to the pci bus. table 9-4 delineates the pci transactions that mu st be performed on the secondary interface. table 9-3. transactions forwarded to pci bus primary interface ? pci express command secondary interface ? pci command memory write request memory write or memory write and invalidate memory read request memory read, memory read line, or memory read line multiple memory read request ? locked memory read, memory read line, or memory read line multiple i/o write request i/o write i/o read request i/o read type 1 configurat ion write request type 0 or type 1 configuration write or special cycle type 1 configuration read request type 0 or type 1 configuration read message request ? vendor-defined n/a message request with data payload ? vendor-defined n/a completion or completion with data n/a table 9-4. transactions performed on secondary interface transaction type pex 8111 initiator on secondary interface pex 8111 target on secondary interface interrupt acknowledge no no special cycle yes no i/o read yes yes i/o write yes yes memory read yes yes memory write yes yes configuration read yes no configuration write yes no memory read line multiple yes yes dual address cycle yes yes memory read line yes yes memory write and invalidate yes yes
bridge operation plx technology, inc. 68 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.4.2 write transactions pci express-to-pci write transactions are po sted or non-posted, as delineated in table 9-5 . the pex 8111 accepts posted transactions without requiring that a completion be returned to the pci express interface. non-posted writes do not generate a completion until the transaction completes on the secondary (pci) bus. memory write request a pci express-to-pci memory write request is performed as a pci memory write or memory write and invalidate transaction. wh en the pex 8111 accepts each pci ex press memory write request tlp, the posted write queue issues a write request, consisting of the following: address (64 bits) byte enables for the first and last dwords tlp total byte count (10 bits) sequence number (6 bits) the pci express base 1.0a states that no tlps can cross a 4-kb address boundary space; therefore, boundary checking does not need be performed when each write request is forwarded to the pci bus. when a tlp crosses a 4-kb addres s boundary space, it is treated as a malformed tlp. when the tlp controller?s posted write data queue fills to cap acity, the pci express master stops sending data. after transaction ordering requirements on the pci bus are met, the pex 8111 requests the secondary pci bus. when the grant is received and the bus is idle, the pex 8111 drives frame#, and the address and command. on the following clock cycle, the firs t data word is driven onto the bus and irdy# is asserted. data is transferred to the pci target wh en trdy# is asserted, and continues transferring until the last word is read from the queue. when a target disconnect is detected, th e current burst terminates. if there is data remaining in the queue, another bu rst write is initiated with the updated address. this burst write continues until the queue is empty, indicating the end of the write transaction. when a pci express-to-pci posted wr ite terminates with a pci target abort, pci master abort, or pci retry abort, the remainder of the data is read from the queue and discarded. an err_nonfatal message is sent to the pci express root complex, if enabled by the pci express device control register non-fatal error reporting enable bit. table 9-5. posted or non-posted pci express writes pci express transaction forwarding memory write request posted i/o write request non-posted type 0 configuration wr ite request not forwarded type 1 configuration write request non-posted
june, 2006 forward bridge pci express-to-pci forwarding (downstream) pex 8111bb expresslane pci express-to-pci bridge data book 69 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 translation to memory write and invalidate the pex 8111 supports translation of pci express memory write requests to pci memory write and invalidate (mwi) transactions. the pci command register memory write and invalidate bit must be set, and the pci cache line size register must be set to a supported value. the mwi command can be used only when the pci express byte enables are contiguous. the address, write request length, and first and last byte enables of each request are used to determine whether an mwi command can be used. the transaction length is loaded into an inte rnal counter and compared to the cache line size. an mwi transaction is initiated when the following three conditions exist: write request contains at l east the number of bytes indicated by the cache line size write request starts at a cache line boundary all byte enables are asserted an internal counter is decremented as each word is transferred to the pci target. at each cache line boundary, the counter is used to determine whether there are at least the number of cache line size bytes remaining. if the necessary number of cache line size bytes are present, the mwi burst continues; otherwise, the mwi terminates and a memory write command transfers the remaining bytes. when a memory write request does not begin or end on a cache line boundary, the request is segmented into multiple transactions. the bytes up to the first cache line boundary are transferred using a memory write comman d. an mwi transaction is then used to transfer the write data beginning on the aligned cache line boundary, including all subsequent complete cache lines up to the final aligned cache line boundary contained in the or iginal memory write request. a memory write transaction is then used to transfer the remaining bytes of the original memory write request. i/o and configuration writes pci express i/o writes and type 1 configuratio n writes are non-posted write transactions. that is , the completion tlp is not returned to the prim ary (pci express) inte rface until the transaction completes on the secondary (pci) interface. th e forwarding address range of the i/o writes is determined by the i/o base and i/o limit registers and bridge control register isa enable and vga enable bits. when the pex 8111 accepts each pci express i/o write or type 1 co nfiguration write request tlp, the non-posted transaction queue issues a write request, consisting of the following: transaction type address (32 bits) byte enables for a single dword tlp total byte count (always a value of 1) sequence number (6 bits) because all i/o writes and type 1 configuration writes are 1 dword in length, this dword is always the first and last dword. these write tran sactions complete on the pci bus, before the completion tlp is returned to the pci express interface. pci express i/o write requests are translated to pci i/o write trans actions. pci express configuration writes are translated to pci co nfiguration transactions. the c onfiguration write address can be modified to indicate a type 0, type 1, or speci al cycle. configuration transaction forwarding is discussed in chapter 8, ?configuration transactions.?
bridge operation plx technology, inc. 70 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 after the transaction ordering requirements are met, the pex 8111 requests the secondary (pci) interface. when the grant is received and the bus is idle, the pex 8111 drives frame#, and the address and command. on the following clock cycle, the data word is driven onto the bus and irdy# is asserted. data is transferred to the pci target when trdy# is asserted, and the transaction terminates. only single words are transferred fo r these transactions. when the tr ansaction successfully completes on the secondary interface, a completion tlp is transmitted to the pci express initiator. when the transaction terminates wi th a master abort, a completion w ith unsupported request status is returned to the pci express interface and the data is discarded. when the transaction terminates with a target ab ort, a completion with completer abort status is returned to the pci express interface and the data is discarded. an err_nonfatal message is sent to the root complex, if enabled by the pci express device control register non-fatal error reporting enable bit. when the transaction term inates with a retry, the pex 8111 re peats the transaction until the data transfer is complete or an error condition is de tected. when the pex 8111 is unable to deliver write data after the number of attempts determined by the pci control register pci express-to-pci retry count field, a completion with completer abort status is returned to the pci express interface, and the data is discarded. a err_nonfatal message is sent to the root complex, if enabled by the pci express device control register non-fatal error reporting enable bit. 9.1.4.3 read transactions pci express-to-pci read transact ions are prefetchable or non-pr efetchable, as delineated in table 9-6 . because a pci express read request always specifies the number of bytes to read, the pex 8111 never reads more data than requested. when translati ng a pci express memory read request into a pci transaction, the pex 8111 uses it s prefetchable and non-prefetchab le memory windows to determine the proper pci read command to use. non-prefetchable memory read transactions when a pci express memory read falls within non-prefetchable addre ss space, the pex 8111 uses the pci memory read command to read the number of bytes requested in the pci express memory read request. the forwarding addr ess range is determined by the memory base , memory limit , prefetchable memory base , and prefetchable memory limit registers and bridge control register vga enable bit. table 9-6. prefetchable or non-prefetchable pci express-to-pci read transactions pci express transaction prefetchable memory read request yes, when in prefetchable space i/o read request non-prefetchable type 0 configuration read request not forwarded type 1 configuration read request non-prefetchable
june, 2006 forward bridge pci express-to-pci forwarding (downstream) pex 8111bb expresslane pci express-to-pci bridge data book 71 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 prefetchable memory read transactions when a pci express memory read falls within pref etchable address space, the pex 8111 uses the pci memory read, memory read line, or memory read line multiple command. the command type is based on the starting address and the number of byte s in the request. the pex 8111 does not extend the length of the burst, but reads the number of bytes requested, as per the pci expressbridge r1.0 . that is , the pex 8111 does not prefetch data from the pci targ et, regardless of whether the data is located in prefetchable memory space. (refer to table 9-7 .) memory read line transactions are terminated at a cache line boundary when there is not at least one cache line of data remaining to read, or if the tr ansaction can be converted to a memory read line multiple transaction. any remaining word s are read, using a me mory read command. memory read request when the pex 8111 accepts each pci express memo ry read request, the no n-posted transaction queue issues a read request, consisting of the following: transaction type (memory read) address (64 bits) byte enables for the first and last dword tlp total byte count of (10 bits) sequence number (6 bits) a memory read, memory read line, or memory read line multiple command is performed on the pci bus, depending upon the starting address, byte enables, and read request length. after the transaction ordering requirements are met, the pex 8111 requests the secondary (pci) interface. when the grant is received and the bus is idle, the pe x 8111 drives frame# and the address and command. on the following clock cycle, irdy# is asserted . read data is transfer red to the pex 8111 when trdy# is asserted, and continues tr ansferring until the read request length is satisfied or the target disconnects. as the data is read from the pci bus, it is written to the non-posted transaction completion queue. when the transaction terminates wi th a master abort, a completion with unsupported request status is returned to the pci express interface. when the transaction terminates with a target abort, a completion with completer abort st atus is returned to the pci express interface. an err_nonfatal messages is sent to the root complex, if enabled by the pci express device control register non-fatal error reporting enable bit. when the transaction term inates with a retry, the pex 8111 repeats the transaction until the data transfer is complete or an error condition is detected. when the pex 8111 is unable to complete the read transaction after the number of attempts specified by the pci control register pci-to-pci express retry count field, a completion with completer abort status is returned to the pci express interface. when a transaction terminates with a pci disconnect, the pex 8111 starts a new read transaction at the current address, and attempts to complete reading the requested number of bytes. after the transaction is complete, a completion is transmitted to the pci express initiator. table 9-7. prefetchable memory read transactions command status memory read used when less than a cache line of data is read. memory read line used when at least one cache line of data is read, and the starting address is not on a cache line boundary. memory read line multiple used when at least one cache line of data is read, and the starting address is on a cache line boundary.
bridge operation plx technology, inc. 72 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 the pex 8111 does not service a new memory read request from the host (performs retries on the pci bus) until it receives a completion from the previ ous read request sent by the host or the pci-to- pci express retry count is exceeded. memory read request locked a pci express memory read request locked is si milar to a normal memory read request. refer to chapter 11, ?exclusive (locked) access,? for details. i/o and configuration reads pci express i/o reads and type 1 configuration reads are non-prefetchab le read transactions. that is , the byte enable information is preserved and no additional bytes are requested. the forwarding address range of the i/o reads is determined by the i/o base and i/o limit registers and bridge control register isa enable and vga enable bits. when the pex 8111 accepts each pci express i/o read or type 1 co nfiguration read request, the non-posted transaction queue issues a r ead request, consisting of the following: transaction type (i/o or configuration type 1 read) address (32 bits) byte enables for a single dword tlp total byte count (always a value of 1) sequence number (6 bits) an i/o read or configuration read command is performed on the pci bus. the configuration read address can be modified to indicate a type 0, type 1, or special cycle. configuration transaction forwarding is discussed in chapter 8, ?configuration transactions.? after the transaction ordering requirements are met, the pex 8111 requests the secondary (pci) interface. when the grant is received and the bus is idle, the pex 8111 drives frame#, and the address and command. on the following clock cycle, irdy# is asserted. read data is transferred to the pex 8111 when trdy# is asserted, and the tran saction terminates. only single dwords are transferred for th ese transactions. when the transaction terminates wi th a master abort, a completion w ith unsupported request status is returned to the pci express interface. when the transaction terminates with a target abort, a completion with completer abort st atus is returned to the pci express interface. an err_nonfatal message is sent to the root complex, if enabled by the pci express device control register non-fatal error reporting enable bit. when the transaction term inates with a retry, the pex 8111 repeats the transaction until the data transfer is complete or an error condition is detected. when the pex 8111 is unable to complete the read transaction after the number of attempts specified by the pci control register pci-to-pci express retry count field, a completion with timeout status is returned to the pci express interface. after the transaction is complete, a completion is transmitted to the pci express initiator. the pex 8111 does not service a new i/o read request or type 1 configuration read from the host (performs retries on the pci bus) until it receives a co mpletion from the previous read request sent by the host or the pci-to-pci express retry count is exceeded.
june, 2006 forward bridge pci-to-p ci express forwarding (upstream) pex 8111bb expresslane pci express-to-pci bridge data book 73 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.5 forward bridge pci-to-pci express forwarding (upstream) 9.1.5.1 transaction types table 9-8 delineates the pci transactions forwar ded upstream to the pci express interface. 9.1.5.2 write decomposition pci write transactions tran sfer byte enables with every data ph ase; however, the pci express interface supports byte enables only on the first and last dwords of a request. furthermore, non-contiguous byte enables are permitted only for requests of 1 or 2 dwords in length, and requests with no byte enables set must use a length of 1 dword. theref ore, in certain cases, the pex 8111 must break up pci write requests into multiple pci express reque sts. byte enables are always set in pci memory write and invalidate transactions; therefore, thes e transactions are not broken up into two separate transactions due to non-contiguous byte enables. pci express write transactions cannot cross 4-kb address boundar ies; therefore, pci writes are terminated with a disconnect at 4-kb boundaries. additionally, pci writes are terminated with a disconnect when the maximu m payload size is reached. 9.1.5.3 read decomposition pci express read transactio ns cannot cross 4-kb address boundaries; therefore, pci reads that cross a 4-kb address boundary space are broken up into mult iple pci express read transactions. when a pci read request crosses a 4-kb address boundary space, the pex 8111 disconnects at the boundary. table 9-8. pci transactions forwarded upstream to pci express interface secondary interface ? pci command primary interface ? pci express command memory write or memory write and invalidate memory write request memory read, memory read line or memory read line multiple memory read request i/o write i/o write request i/o read i/o read request
bridge operation plx technology, inc. 74 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.5.4 pci express header field formation rules table 9-9 delineates the pci express header field formation rules. 9.1.5.5 requester id and tag the pex 8111 uses the bus number (from the secondary bus number register), device number (always a value of 0), and function number (always a value of 0) to create the requester id. the 8-bit tag is created by the tlp controller , and is unique for each transaction. table 9-9. pci express header field formation rules header item rule fmt[1:0] single address pci cycles (below the 4-gb address boundary space) use a 3-dword header. dual address cycles (at or above the 4-gb boundary) use a 4-dword header. write requests use a request format with data. type[4:0] populated, based upon the command translations described in section 9.1.4.1, ?transaction types.? tc[3:0] for requests, this field mu st be cleared to 0. for completions, this field must contain the value supplied in the corresponding request. attr[1:0] these bits include the relaxed ordering and no snoop attributes. always cleared to 0. td cleared to 0. the pex 8111 does not support ecrc in the tlp digest. ep set to 1 when the pex 8111 is forwarding an uncorrectable data error from the pci bus. length[9:0] pci write or read reque st length, rounded up to nearest dword-aligned boundary. requester id[15:0] assigned by the pex 8111, comprised of the bus, device and function numbers. tag[7:0] sequentially assigned by the pex 8111. first dword byte enable[3:0] and last dword byte enable[3:0] first and last byte enables. address[63:2] (4-dword header) or address[31:2] (3-dword header) transaction dword starting address. value is derived from the byte address of the pci transaction, by rounding the address down to the nearest dword-aligned boundary. requester id tag 15 8 7 3 2 0 7 0 bus number device number function number tag
june, 2006 forward bridge pci-to-p ci express forwarding (upstream) pex 8111bb expresslane pci express-to-pci bridge data book 75 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.5.6 memory write or me mory write and invalidate memory write or memory write and invalidate tran sactions are performed as a pci express memory write request. the forwarding address range is determined by the memory base , memory limit , prefetchable memory base , and prefetchable memory limit registers and bridge control register vga enable bit. writes cannot cross 4-kb address boundaries. write data posting is required for these transactions. the pex 8111 terminates these trans actions with a retry when the pex 8111 is locked from the pci express interface. when the pex 8111 determines that a pci write transaction is to be forwarded to the pci express interface, devsel# and trdy# are asserted, assuming that there is sufficient space in the 8-dword buffer. when there is insufficient buffer space, the pex 8111 responds with a retry. when there is sufficient space, the pex 8111 accepts writ e data until one of the following occurs: pci initiator terminates the transaction by de-asserting frame# 4-kb address boundary space is reached buffer fills and the secondary latency timer (forward bridge mode) or pci bus latency timer (reverse bridge mode) times out maximum payload size is reached no byte enables, or partial byte enab les, are detected during memory write when one of these events occurs, the pex 8111 termin ates the pci transaction with a disconnect. if no byte enables, or partial byte enables, are assert ed during a dword transaction, the write transaction must be broken up into two separate transactions. the data with no byte enables, or partial byte enables and the corresponding address are wri tten into the posted write data queue as a new transaction. the tlp controller prioritizes th ese transactions. when the posted write?s sequence number is less than that of the non-post ed transaction, the posted write is performed first. when the posted write?s sequence number is greater than that of the non-posted transac tion, the transactions alternate. 9.1.5.7 delayed transactions non-posted pci transactions (except memory write transactions) are performed as delayed transactions on the pci bus. a delayed transac tion occurs when the pex 8111 responds to a non- posted transaction with a retry, and forwards th e request to the pci express interface. when the associated completion returns from the pci express target, the pex 8111 buffers the completion until the pci initiator retries the transaction. the following information is latched from the pci bus and stored into the non-posted tr ansaction queue when a new dela yed transaction is detected: address address parity command byte enables data for write transactions data parity for write transactions after latching the above information, the pci transaction terminates with a retry. the pex 8111 then transmits the delayed transaction reques t upstream to the pci express interface: when the delayed request is a read (memory, i/o, or configuration), the r ead data is read from the pci express interface and st ored in the tlp controller. when the delayed request is a write (i/o or configuration), the write data is delivered to the pci express target.
bridge operation plx technology, inc. 76 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 at the completion of a delayed read, the request in the non-posted transaction queue is tagged as complete . the request is removed from the non-posted transaction queue when the transaction is retried and completed on the pci bus. the pex 8111 differentiates between pci transactions by comparing the current transaction with the transaction stored in the non-post ed transaction queue. when the bridge control register secondary parity error response enable bit is cleared to 0, the address and data parity bits are ignored during the comparison. the byte enables are ignored when the read is from the prefetchable memory space. when the compare matches a non-post ed transaction queue entry, but the transaction is not completed on the pci express interface, the transaction is not re -queued, but terminates with a retry. when the compare matches a non-posted transaction queue en try, and the transaction completed on the pci express interface, the transaction completes on the pci bus. for a non-posted write, trdy# is returned, thereby completing the transaction. for a read transactio n, read data is returned to the pci initiator. the pex 8111 can queue up to four delayed transact ions. these transactions are performed on the pci express interface in the order that they occurred on the pci bu s. after non-posted writes are completed on the pci express interface, they are co mpleted on the pci bus in the order that the pci initiator retries them. non-posted reads are always completed on the pci bus in the order they complete on the pci express interface. a bridge is permitted to discard a delayed request. the pex 8111 never discards a delayed request that is not completed on the pci express interface. a brid ge is allowed to discard a delayed completion in the following two cases only: if prefetched data remains in the delayed read data queue when the pci initiator terminates the read transaction, the data is discarded. each entry in the non-posted tran saction queue has an associated secondary discard timer . the timer is activated when a read or write tr ansaction completes on th e pci express interface. if the pci initiator does not retry the delayed transaction before the timer times out, the delayed request and completion are removed fr om the non-posted tr ansaction queue. the bridge control register discard timer status bit is set. in addition, the pex 8111 transmits an error message to the pci expre ss interface, if enabled, by the bridge control register discard timer serr# enable and pci command register serr# enable bits. 9.1.5.8 memory read, memory read li ne, or memory read line multiple memory read, memory read line, or memory read line multiple transactions are performed as a pci express memory read request. the forwar ding address range is determined by the memory base , memory limit , prefetchable memory base , and prefetchable memory limit registers and bridge control register vga enable bit. reads cannot cross 4-kb address boundaries. this transaction is performed as a de layed transaction on the pci bus. when the pex 8111 determines that a pci read transaction is to be forwarded to the pci express interface, devsel# and stop# are asserted, indicating a retry. the address, address parity, command, and byte enables are stored in an entry in the non-posted trans action queue, assuming that there is sufficient space in the queue. if there is in sufficient space, the trans action is retried without entering the transact ion into the queue. after the request reaches the top of the non-posted transaction qu eue, a memory read request is transmitted to the pci express interface. the number of bytes requested from the pci express interface is determined by the pci comm and, the address space, and the device-specific control register blind prefetch enable bit. (refer to table 9-10 .)
june, 2006 forward bridge pci-to-p ci express forwarding (upstream) pex 8111bb expresslane pci express-to-pci bridge data book 77 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 when the starting address and read request length causes the read to cross a 4-kb address boundary space, the read request length is truncated so the 4-kb address boundary space is not crossed. when the read request length is greater than the value of the pci express device control register maximum read request size field, the request length is truncated to the specified size. when the read is to non-prefetchable memory, the byte enables ar e passed from the pci bus. when the read is to prefetchable memory, all byte enables ar e asserted in the pci express request. when the memory read request does not successful ly complete on the pci express interface, the read request entry in the non-posted transaction queue is appropriatel y marked. when the transaction is retried on the pci bus, it terminates with a targ et abort response. when the memory read request successfully completes on the pci express interf ace, the read request entry in the non-posted transaction queue is marked as complete . when the transaction successfully co mpletes on the pci express interf ace, and all ordering constraints with posted write transactions are satisfied, the pex 8111 transfers data to the pci initiator when the initiator retries the transaction. the pex 8111 asserts trdy# and drives data until the final dword is transferred from the queue to the pci initiator. when the initiator terminates the transaction before all queue data is transferred, the remaining da ta is read from the queue and discarded. blind prefetch when blind prefetch mode is enabled ( device-specific control register blind prefetch enable bit is set), the pex 8111 can prefetch a user-defined data block from the host when a memory read transaction is performed, instead of one dword at a time in standard operation. prefetching can improve read performance, b ecause the pex 8111 can burst its prefetchable data onto the pci bus when the endpoint requests it. the pex 8111 discards remaining unused data. the prefetch size can be programmed from 0 to 4 kb of data, by way of the pci control register programmed prefetch size field. table 9-10. bytes requested by pci express interface determined by pci command, address space, register, and bit after request reaches top of queue pci transaction address space blind prefetch enable number of dwords requested memory read non-prefetchable ? 1 prefetchable 0 1 prefetchable 1 cache line size memory read line ? ? cache line size memory read line multiple ? ? 2 cache line sizes
bridge operation plx technology, inc. 78 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.5.9 i/o write i/o write transactions ar e performed as a pci express i/o write request. the forwarding address range is determined by the i/o base and i/o limit registers and bridge control register isa enable and vga enable bits. this transaction is performed as a dela yed transaction on the pci bus. posting these transactions is not permitted. a completion must be received from the pci express target before the transaction is completed on the pci bus. when the pex 8111 determines that a pci i/o write transaction is to be forwarded to the pci express interface, devsel# and stop# are asserted, indicating a retry. the address, address parity, command, data, data parity, and by te enables are stored into an en try in the non-posted transaction queue, assuming that there is sufficient space in the que ue. if there is insufficient space, the transaction is retried without entering the transaction into the queue. after the request reaches the top of the non-po sted transaction queue, an i/o write request is transmitted to the pci express interface. the byte enables are passed through from the pci bus, and only 1 dword is transferred. when the write request does not successfully comple te on the pci express interface, the write request entry in the non-posted transaction queue is appropr iately marked. when the transaction is retried on the pci bus, it terminates with a target abort response. when the i/o write request successfully completes on the pci express interface, the i/o write request entry in the non-posted transaction queue is marked as complete . when the transaction successfully completes on the pci express interface, the pex 8111 asserts trdy# to complete the transaction when the initiator retries the transaction. the i/o write request is removed from the non-posted transaction queue when the pci initiator retries the transaction and the transaction completes (su ccessfully or not) on the pci express interface. 9.1.5.10 i/o read i/o read transactions are performed as a pci expr ess i/o read request. the forwarding address range is determined by the i/o base and i/o limit registers and bridge control register isa enable and vga enable bits. this transaction is performed as a delayed transaction on the pci bus. when the pex 8111 determines that a pci i/o read tr ansaction is to be forwarded to the pci express interface, devsel# and stop# are asserted, indica ting a retry. the addr ess, command, address parity, and byte enables ar e stored into an entry in the non-po sted transaction queue, assuming that there is sufficient space in the queue. if there is in sufficient space, the trans action is retried without entering the transact ion into the queue. after the request reaches the top of the non-posted tr ansaction queue, an i/o read request is transmitted to the pci express interface. the byte enables are passed through from the pci bus, and only 1 dword is requested. when all ordering constr aints with posted write tr ansactions are satisfied, the pex 8111 transfers data to the pci initiator when the initiator retries the transaction. the pex 8111 asserts trdy# and drives a single dword of data from the queue to the pci initiator. if the i/o read request does not successfully complete on the pci ex press interface, the read request entry in the non-posted transaction queue is appropr iately marked. when the transaction is retried on the pci bus, it terminates with a target abor t response. when the i/o read request successfully completes on the pci express interface, the read requ est entry in the non-posted transaction queue is marked as complete .
june, 2006 forward bridge pci transaction terminations pex 8111bb expresslane pci express-to-pci bridge data book 79 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.6 forward bridge pci transaction terminations table 9-11 delineates the transaction termina tion methods used by pci initiators. table 9-12 delineates the transaction termination methods used by pci targets. table 9-11. pci initiator transaction termination methods termination methods description normal termination the initiator de-asserts fr ame# at the beginning of the last data phase and de-a sserts irdy# at the end of the last data phase if the target asserts trdy# or stop#. master abort if the initiator does not dete ct devsel# asserted from the target within five clock cycles after asserting frame#, the transaction terminates with a master abort. if frame# remains asserted, the initiator de- asserts frame# on the next cycle, then de-asserts irdy# on the following cycle. irdy# must be asserted in the same cycle in which frame# de-asserts. if frame# is de-asserted, ir dy# can be de-asserted on the next clock cycle followi ng detection of the master abort condition. table 9-12. pci target transaction termination methods termination methods description normal termination trdy# and devsel# are as serted in conjunction with frame# de-assertion and irdy# assertion. target retry stop# and devsel# assert ed without trdy# during the first data phase. no data transfers occur during the transaction, and the initiator must repeat the transaction. target disconnect with data stop# and devsel# assert ed with trdy#, which indicates that this is the last transfer of the transaction. if frame# is de-asserted, this is considered a normal termination, although stop# is asserted. target disconnect without data stop# and devsel# are asserted without trdy# after previous data transfer s occurred, which indicates that no further data transfers occur during this transaction. target abort stop# is asserted wit hout devsel# and trdy#, which indicates that the target is never able to complete this transaction. devsel# must be asserted for at least one clock cycle during the transaction; otherwise, the initiator detects a master abort.
bridge operation plx technology, inc. 80 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.6.1 pci master termi nation initiated by pex 8111 the pex 8111, as a pci initiator, uses normal termination if the target asserts devsel# within five clock cycles of frame# assertion. as an initiato r, the pex 8111 terminates a transaction when any of the following occur: during a delayed write transact ion (i/o or configuration write), a single dword is delivered during a non-prefetchable read (memory, i/o, or configuration), a single dword is read from the target in the case of a prefetchable read transaction, the number of wo rds requested in the pci express request are read from the pci target in the case of a posted write tr ansaction, the last word for the transaction is written to the pci target in the case of a burst transfer, with the exceptio n of memory write and invalidate transactions, the master latency timer expires and the pci bus grant is de-asserted the target terminates the tr ansaction with a retry, di sconnect, or target abort when a posted write or prefetchable read transaction terminates becau se of a latency timeout, another transaction is initiated to complete the transfer. 9.1.6.2 pci master abor t received by pex 8111 when the pex 8111, as a pci initia tor, does not detect devsel# asse rted from the target within five clock cycles after asserting fram e#, the pex 8111 termin ates the transaction with a master abort. in forward bridge mode, the secondary status register secondary received master abort bit is set. in reverse bridge mode, the pci status register received master abort bit is set. refer to chapter 10, ?error handling,? and chapter 11, ?exclusive (locked) access,? for further details.
june, 2006 forward bridge pci transaction terminations pex 8111bb expresslane pci express-to-pci bridge data book 81 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.6.3 delayed write ta rget termination response when the pex 8111 initiates a dela yed write transaction on the pci bu s, it responds to certain target terminations as delineated in table 9-13 . 9.1.6.4 posted write targ et termination response when the pex 8111 initiates a posted write transact ion on the pci bus, it responds to certain target terminations as delineated in table 9-14 . table 9-13. pex 8111 response to target terminations upon delayed write transactions target termination pex 8111 response normal return completion with successful completion status to the pci express interface. target retry repeat write transaction for up to 2 24 attempts. target disconnect return completion with successful completion status to the pci express interface. target abort return completion with completer abort status to the pci express interface. discard delayed write request. forward bridge mode ? set the secondary status register secondary received target abort bit. reverse bridge mode ? set the pci status register received target abort bit. table 9-14. pex 8111 response to target terminations upon posted write transactions target termination pex 8111 response normal no action. target retry repeat write transa ction for up to 2 24 attempts. target disconnect initiate write transaction to deliver remaining posted write data. target abort discard posted write data. forward bridge mode ? set the secondary status register secondary received target abort bit. reverse bridge mode ? set the pci status register received target abort bit.
bridge operation plx technology, inc. 82 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.6.5 delayed read ta rget termination response when the pex 8111 initi ates a delayed read transaction on the pci bus, it responds to certain target terminations as delineated in table 9-15 . 9.1.6.6 target retry initiated by pex 8111 the pex 8111 returns a target retry to a pci initiator when any of the following conditions are met: delayed write transactions ? transaction is entering the non-posted transaction queue ? transaction is stored into the non-posted transaction qu eue; however the transaction is not completed on the pci express interface ? non-posted transaction queue is full , and the transaction cannot be queued ? transaction with the same address and bus command is queuing ? locked sequence is propagated across the pe x 8111, and the write transaction is not a locked transaction delayed read transactions ? transaction is entering the non-posted transaction queue ? transaction is stored in th e non-posted transaction queue , but the read data is not yet available ? read was received from the pci express inte rface; however, a posted write transaction precedes it ? non-posted transaction queue is full , and the transaction cannot be queued ? transaction with the same address and bus command was queued ? locked sequence is propagated across the pe x 8111, and the read transaction is not a locked transaction ? pex 8111 is currently discarding previously prefetched read data posted write transactions ? pci-to-pci express 8-dword write buffer is not empty ? locked sequence is propagated across the pe x 8111, and the write transaction is not a locked transaction table 9-15. pex 8111 response to target terminations upon delayed read transactions target termination pex 8111 response normal return completion with successful completion status to the pci express interface. target retry repeat read transaction for up to 2 24 attempts. target disconnect initiate read transa ction to obtain rema ining read data. target abort return completion with completer abort status to the pci express interface. discard delayed read request. forward bridge mode ? set the secondary status register secondary received target abort bit. reverse bridge mode ? set the set the pci status register received target abort bit.
june, 2006 forward bridge pci transaction terminations pex 8111bb expresslane pci express-to-pci bridge data book 83 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.1.6.7 target disconnect initiated by pex 8111 the pex 8111 returns a target disconnect to a pci initiator when any of the following conditions are met: a 4-kb address boundary space or cache line boundary is reached 8-dword posted write buffer fills and the secondary latency timer (forward bridge mode) or pci bus latency timer (reverse bridge mode) times out 8-dword read buffer becomes empty and the secondary latency timer (forward bridge mode) or pci bus latency timer (reverse bridge mode) times out maximum payload size is reached byte enables not set for posted write 9.1.6.8 target abort initiated by pex 8111 the pex 8111 returns a target abort to a pci initiator when the pex 8111 is unable to obtain read data from, or write data to, the pci express interface. refer to chapter 10, ?error handling,? for further details.
bridge operation plx technology, inc. 84 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.2 reverse bridge operation in reverse bridge mode, the pex 8111 presents a type 1 configuration space header on the pci bus. there are no pci-compatible configuration registers available on the pci express interface. three sets of type 1 configuration space head er registers define the bridging operation between the pci bus and pci express interface. (refer to table 9-16 .) the pex 8111 also supports one pci base address re gister (bar), which allows a pci express or pci master to access internal configuration registers or shared memory. during bus enumeration, the addresses corresponding to the bar are excluded fr om the bridging ranges of the six registers referenced in table 9-16 . table 9-16. type 1 configuration space header register sets that define bridging operation between pci bus and pci express interface register set description i/o base and i/o limit when i/o transactions on the pci bus fall within the range specified by these registers, the transactions are forwarded to the pci express interface. when i/o transactions on the pci express interface fall outside the range specified by these registers, the transactions are forwarded to the pci bus. memory base and memory limit when non-prefetchable memory transacti ons on the pci bus fall within the range specified by these registers, the transactions are forwarded to the pci express interface. when non-prefetchable memory transactions on the pci express interface fall outside the range specified by these registers, the transactions are forwarded to the pci bus. prefetchable memory base and prefetchable memory limit when prefetchable memory transactions on the pci bus fall within the range specified by these registers, the transactions are forwarded to the pci express interface. when prefetchable memory transactions on the pci express interface fall outside the range specified by these registers, the transactions are forwarded to the pci bus.
june, 2006 reverse bridge pci-to-p ci express forwarding (downstream) pex 8111bb expresslane pci express-to-pci bridge data book 85 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 9.2.1 reverse bridge pci-to-pci express forwarding (downstream) 9.2.1.1 transaction types table 9-17 delineates the pci transactions fo rwarded to the pci express interface. table 9-18 delineates the pci transactions perfor med on the primary interface. the data paths and control logic for reverse bridge mode are the same as thos e used for forward bridge mode, except that address decoding based upon the configuration registers are located on the pci bus. table 9-17. pci transactions forwarded to pci express interface primary interface ? pci command secondary interface ? pci express command memory write or memory write and invalidate memory write request memory read, memory read line, or memory read line multiple memory read request memory read, memory read line, or memory read line multi ple, lock# asserted memory read request ? locked i/o write i/o write request i/o read i/o read request type 1 configuration write type 0 or type 1 configuration write request type 1 configuration read type 0 or type 1 configuration read request table 9-18. pci transactions performed on primary interface transaction pex 8111 initiator on primary interface pex 8111 target on primary interface interrupt acknowledge no no special cycle no no i/o write yes yes i/o read yes yes memory write yes yes memory read yes yes configuration write no yes configuration read no yes memory write and invalidate yes yes memory read line yes yes memory read line multiple yes yes dual address cycle yes yes
bridge operation plx technology, inc. 86 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 87 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 10 error handling 10.1 forward bridge error handling for all errors detected by the pex 8111, it sets th e appropriate error status bit [both legacy pci error bit(s) and pci express error status bit(s)], and opt ionally generates an error message on pci express. each error condition has a default error severity level, with a corresponding error message generated on pci express. error message generation on the pci express interface is contro lled by four control bits: pci command register serr# enable bit pci express device control register fatal error reporting enable bit pci express device control register non-fatal error reporting enable bit pci express device control register correctable error reporting enable bit pci express err_fatal messages are enabled for transmission when the serr# enable or fatal error reporting enable bit is set. err_nonfatal messages ar e enabled for transmission when either the serr# enable or non-fatal error reporting enable bit is set. err_cor messages are enabled for transmission when the correctable error reporting enable bit is set. the pci express device status register fatal error detected , non-fatal error detected , and correctable error detected status bits are set for the correspondi ng errors on pci express, regardless of the error reporting enable bits. 10.1.1 forward bridge pci ex press originating interface (primary to secondary) this section describes error support for transactions that cross the pex 8111 when the originating side is the pci express interface, and the destination si de is the pci bus. when a write request or read completion is received with a poisoned tlp, the entire data payload of the pci express transaction must be considered as corrupt. invert the parity for all data when completing the transaction on the pci bus. table 10-1 provides the translation a bridge must perf orm when it forwards a non-posted pci express request (read or write) to the pci bus, and the requ est is immediately completed on the pci bus, either normally or with an error condition. table 10-1. translation performed when bridge forwards a non-posted pci express request immediate pci termination pci express completion status data transfer with parity erro r (reads) successful (poisoned tlp) completion with parity error (n on-posted writes) unsupported request master abort unsupported request target abort completer abort
error handling plx technology, inc. 88 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.1.1.1 received poisoned tlp when the pex 8111 pci express interface receives a wr ite request or read completion with poisoned data, the following occur: pci status register detected parity error bit is set pci status register master data parity error bit is set when the poisoned tlp is a read completion and the pci command register parity error response enable bit is set err_nonfatal message is generated on pci e xpress, when the following conditions are met: ? pci command register serr# enable bit is set ?or? ? pci express device control register non-fatal error reporting enable bit is set pci status register signaled system error bit is set when the serr# enable bit is set parity bit associated with each dword of data is inverted for a poisoned write request, the secondary status register secondary master data parity error bit is set when the bridge control register secondary parity error response enable bit is set, and the pex 8111 sees perr# asserted when the inverted parity is detected by the pci target device 10.1.1.2 pci uncorrectable data errors the following sections describe how errors are ha ndled when forwarding non-poisoned pci express transactions to the pci bus, and an uncorrectable pci error is detected. immediate reads when the pex 8111 forwards a read request (i/o, memory, or configuration) from the pci express and detects an uncorrectable data error on the secondary bus whil e receiving an immediate response from the completer, the following occur: secondary status register secondary master data parity error bit is set when the bridge control register secondary parity error response enable bit is set secondary status register secondary detected parity error bit is set perr# is asserted on the secondary interface when the bridge control register secondary parity error response enable bit is set after detecting an un correctable data erro r on the destination bus for an immediate read transaction, the pex 8111 continues to fetch data until the byte count is satisfied or the target ends the transaction. when the pex 8111 creates the pci express completion, it forwards it with successful completion and poisons the tlp. posted writes when the pex 8111 detects perr# asserted on the pci secondary interface while forwarding a non-poisoned posted write transaction fr om pci express, the following occur: secondary status register secondary master data parity error bit is set when the bridge control register secondary parity error response enable bit is set err_nonfatal message is generated on pci e xpress, when the following conditions are met: ? pci command register serr# enable bit is set ?or? ? pci express device control register non-fatal error reporting enable bit is set pci status register signaled system error bit is set when the serr# enable bit is set after the error is detected, the remainder of the data is forwarded
june, 2006 forward bridge pci express originating interface (primary to secondary) pex 8111bb expresslane pci express-to-pci bridge data book 89 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 non-posted writes when the pex 8111 detects perr# asserted on the pci secondary interface while forwarding a non-poisoned non-posted write transaction from pci express, the following occur: secondary status register secondary master data parity error bit is set when the bridge control register secondary parity error response enable bit is set pci express completion with unsuppor ted request status is generated err_nonfatal message is generated on pci e xpress, when the following conditions are met: ? pci command register serr# enable bit is set ?or? ? pci express device control register non-fatal error reporting enable bit is set pci status register signaled system error bit is set when the serr# enable bit is set 10.1.1.3 pci address errors when the pex 8111 forwards trans actions from pci express-to-pci, pci address errors are reported by serr# assertion. when the pex 8111 detects serr# asserted, the following occur: secondary status register secondary received system error bit is set err_fatal message is generated on pci expr ess, when the following conditions are met: ? bridge control register secondary serr# enable bit is set ? pci command register serr# enable bit or pci express device control register fatal error reporting enable bit is set pci status register signaled system error bit is set when the secondary serr# enable and serr# enable bits are set 10.1.1.4 pci master abort on posted transaction when a posted write transaction fo rwarded from pci express-to-pci re sults in a master abort on the pci bus, the following occur: entire transaction is discarded secondary status register secondary received master abort bit is set err_nonfatal message is generated on pci e xpress when the following conditions are met: ? bridge control register master abort mode bit is set ? pci command register serr# enable bit or pci express device control register non-fatal error reporting enable bit is set pci status register signaled system error bit is set when the master abort mode and serr# enable bits are set 10.1.1.5 pci master abor t on non-posted transaction when a non-posted transaction forw arded from pci express-to-pci re sults in a master abort on the pci bus, the following occur: completion with unsupported request status is returned on pci express secondary status register secondary received master abort bit is set
error handling plx technology, inc. 90 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.1.1.6 pci target ab ort on posted transaction when a transaction forwarded from pci express-to-pci results in a ta rget abort on the pci bus, the following occur: entire transaction is discarded secondary status register secondary received target abort bit is set err_nonfatal message is generated on pci e xpress when the following conditions are met: ? pci command register serr# enable bit is set ?or? ? pci express device control register non-fatal error reporting enable bit is set pci status register signaled system error bit is set when the serr# enable bit is set 10.1.1.7 pci target abor t on non-posted transaction when a transaction forwarded from pci express-to-pci results in a ta rget abort on the pci bus, the following occur: completion with completer abort status is returned on the pci express secondary status register secondary received target abort bit is set pci status register signaled target abort bit is set err_nonfatal message is generated on pci e xpress when the following conditions are met: ? pci command register serr# enable bit is set ?or? ? pci express device control register non-fatal error reporting enable bit is set pci status register signaled system error bit is set when the serr# enable bit is set 10.1.1.8 pci retry abor t on posted transaction when a transaction forwarded from pci express-to-pci results in the maximum number of pci retries (selectable in the pci control register), the following occur: remaining data is discarded interrupt re quest status register pci express-to-pci retry interrupt bit is set 10.1.1.9 pci retry abor t on non-posted transaction when a transaction forwarded from pci express-to-pci results in the maximum number of pci retries (selectable in the pci control register), the following occur: completion with the completer abort status is returned on pci express interrupt re quest status register pci express-to-pci retry interrupt bit is set pci status register signaled target abort bit is set
june, 2006 forward bridge pci originating interface (secondary to primary) pex 8111bb expresslane pci express-to-pci bridge data book 91 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.1.2 forward bridge pc i originating interface (secondary to primary) this section describes error support for transactions that cross the pex 8111 when the originating side is the pci bus, and the destination side is pci express. the pex 8111 supports tlp poisoning as a transmitter to permit proper forwardi ng of parity errors that occur on the pci interface. posted write data received on the pci interface with bad parity is forwarded to pci express as poisoned tlps. table 10-2 provides the error forwarding requirements for uncorrectable data errors detected by the pex 8111 when a tran saction targets the pci express interface. table 10-3 describes the pex 8111?s behavior on a pci delayed transaction that is forwarded by a bridge to pci express as a memory read request or an i/o read/write request, and the pci express interface returns a comple tion with ur or ca status for the request. table 10-2. error forwarding requirements received pci error forwarded pci express error write with parity error write request with poisoned tlp read completion with parity error in da ta phase read completi on with poisoned tlp configuration or i/o completion with parity error in data phase read/write completion with completer abort status table 10-3. pex 8111 behavior on a pci delayed transaction pci express completion status pci immediate response master abort mode = 1 master abort mode = 0 unsupported request (on memory read or i/o read) target abort normal completion, return ffff_ffffh unsupported request (on i/o write) target abort normal completion completer abort target abort
error handling plx technology, inc. 92 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.1.2.1 received pci errors uncorrectable data error on non-posted write when a non-posted write is addressed such that it crosses the pex 8111, and the pex 8111 detects an uncorrectable data error on the pci interface, the following occur: secondary status register secondary detected parity error status bit is set. if the bridge control register secondary parity error response enable bit is set, the transaction is discarded and is not forwarded to pci express. the perr# signal is asserted on the pci bus. if the bridge control register secondary parity error response enable bit is not set, the data is forwarded to pci express as a poisoned tlp. also, set the pci status register master data parity error bit when the pci command register parity error response enable bit is set. the perr# signal is not asserted on the pci bus. uncorrectable data error on posted write when the pex 8111 detects an uncorrectable data error on the pci secondary interface for a posted write transaction that crosses th e pex 8111, the following occur: pci perr# signal is asserted when the bridge control register secondary parity error response enable bit is set secondary status register secondary detected parity error status bit is set posted write transaction is forwarde d to pci express as a poisoned tlp pci status register master data parity error bit is set when the pci command register parity error response enable bit is set uncorrectable data error on pci delayed read completions when the pex 8111 forwards a non-poisoned r ead completion from pci express-to-pci, and it detects perr# asserted by the pci master, th e remainder of the completion is forwarded. when the pex 8111 forwards a poisoned read co mpletion from pci express-to-pci, the pex 8111 proceeds with the above mentioned actions when it detects the perr# signal asserted by the pci master; however, no error messa ge is generated on pci express. uncorrectable address error when an uncorrectable addr ess error is detected by the pex 8111, and parity error detection is enabled by way of the bridge control register secondary parity error response enable bit, the following occur: transaction is terminated with a target abort secondary status register secondary detected parity error status bit is set, independent of the setting of the bridge control register secondary parity error response enable bit secondary status register secondary signaled target abort bit is set err_fatal message is generated on pci expr ess when the following conditions are met: ? pci command register serr# enable bit is set ?or? ? pci express device control register fatal error reporting enable bit is set pci status register signaled system error bit is set when the serr# enable bit is set
june, 2006 forward bridge pci originating interface (secondary to primary) pex 8111bb expresslane pci express-to-pci bridge data book 93 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.1.2.2 unsupported request (ur) completion status the pex 8111 provides two methods for hand ling a pci express co mpletion received with unsupported request (ur) status in response to a re quest originated by the pci interface. the response is controlled by the bridge control register master abort mode bit. in either case, the pci status register received master abort bit is set. master abort mode bit cleared this is the default pci compatibility mode, and an unsupported request is not considered to be an error. when a read transaction initiated on the pci results in the return of a completion with unsupported request status, the pex 8111 returns ffffffffh to the originating master and terminates the read transaction on the originating inte rface normally (by asserting trdy#). when a non-posted write transaction results in a completion with unsupported request status, the pex 8111 completes the write transaction on the originating bus normally (by asserting trdy#) and discards the write data. master abort mode bit set when the bridge control register master abort mode bit is set, the pex 8111 signals a target abort to the originating master of an upst ream read or non-posted write transaction when the corresponding request on the pci express interface results in a completion with ur stat us. in addition, the secondary status register secondary signaled target abort bit is set. 10.1.2.3 completer abort (ca) completion status when the pex 8111 receives a completion with comp leter abort status on the pci express primary interface in response to forwarded non-posted pci transactions, the pci status register received target abort bit is set. a ca response can result in a delayed transaction target abort on the pci bus. the pex 8111 provides data to the requesting pci ag ent, up to the point where data was successfully returned from the pci express interf ace, then signals target abort. the secondary status register secondary signaled target abort bit is set when signaling target abort to a pci agent.
error handling plx technology, inc. 94 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.1.3 forward bridge timeout errors 10.1.3.1 pci express completion timeout errors the pci express completion timeout mechanism allows requesters to abort a non-posted request when a completion does not arrive within a reasonable length of time. bridges, when acting as initiators on pci express on behalf of internally generated reques ts or when forwarding requests from a secondary interface, behave as endpoints for requests of which they take ownership. when a completion timeout is det ected and the link is up , the pex 8111 responds as if a completion with unsupported request status is received. the following action is taken: err_nonfatal message is generated on pci e xpress when the following conditions are met: ? pci command register serr# enable bit is set ?or? ? pci express device control register non-fatal error reporting enable bit is set pci status register signaled system error bit is set when the serr# enable bit is set when the link is down, the pci control register pci express-to-pci retry count field determines the number of pci retries before a master abort is returned to the pci bus. 10.1.3.2 pci delayed transaction timeout errors the pex 8111 includes delayed transaction time rs for each queued delayed transaction. when a delayed transaction timeout is detected, the following occur: err_nonfatal message is generated on pci e xpress when the following conditions are met: ? bridge control register discard timer serr# enable bit is set ? pci command register serr# enable bit or pci express device control register non-fatal error reporting enable bit is set pci status register signaled system error bit is set when the serr# enable bit is set bridge control register discard timer status bit is set 10.1.4 forward bridge ?other? errors pci devices assert serr# when det ecting errors that compromise syst em integrity. when the pex 8111 detects serr# asserted on the second ary (pci) bus, the following occur: secondary status register secondary received system error bit is set err_fatal message is generated on pci express, when the following conditions are met: ? bridge control register secondary serr# enable bit is set ? pci command register serr# enable bit or pci express device control register fatal error reporting enable bit is set pci status register signaled system error bit is set when the secondary serr# enable and serr# enable bits are set
june, 2006 reverse br idge error handling pex 8111bb expresslane pci express-to-pci bridge data book 95 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.2 reverse bridge error handling for all errors detected by the pex 8111, it sets th e appropriate error status bit [both legacy pci error bit(s) and pci express error status bit(s)]. pci express error messages are not generated in reverse bridge mode. 10.2.1 reverse bridge pci ex press originating interface (secondary to primary) this section describes error support for transactions that cross the pex 8111 when the originating side is the pci express (secondary) in terface, and the destination side is the pci (primary) interface. table 10-4 provides the translation the pex 8111 performs when it forwards a non-posted pci express request (read or write) to the pci bus, and the requ est is immediately completed on the pci bus, either normally or with an error condition. 10.2.1.1 received poisoned tlp when a write request or read co mpletion is received by the pci express interface, and the data is poisoned, the following occur: secondary status register secondary detected parity error bit is set secondary status register secondary master data parity error bit is set when the poisoned tlp is a read completion and the bridge control register secondary parity error response enable bit is set parity bit associated with each dword of data is inverted for a poisoned write request, the pci status register master data parity error bit is set when the pci command register parity error response enable bit is set, and the pex 8111 sees perr# asserted when the inverted parity is detected by the pci target device table 10-4. pex 8111 translation ? non-posted pci request immediate pci termination pci express completion status data transfer with parity error (reads) successful (poisoned tlp) completion with parity error (n on-posted writes) unsupported request master abort unsupported request target abort completer abort
error handling plx technology, inc. 96 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.2.1.2 pci uncorrectable data errors the following sections describe how errors are ha ndled when forwarding non-poisoned pci express transactions to the pci bus, and an uncorrectable pci error is detected. immediate reads when the pex 8111 forwards a read request (i /o or memory) from the pci express secondary interface and detects an uncorrectable data error on the pc i primary bus while r eceiving an immediate response from the completer, the following occur: pci status register master data parity error bit is set when the pci command register parity error response enable bit is set pci status register detected parity error bit is set perr# is asserted on the pci interface when the pci command register parity error response enable bit is set after detecting an un correctable data error on the destinati on bus for an immediate read transaction, the pex 8111 continues to fetch data until the byte count is satisfied or the target ends the transaction. when the pex 8111 creates the pci express comple tion, it forwards it w ith successful completion status and poisons the tlp. non-posted writes when the pex 8111 detects pe rr# asserted on the pci prim ary interface while forwarding a non-poisoned non-posted write transaction from pci express, the following occur: pci status register master data parity error bit is set when the pci command register parity error response enable bit is set pci express completion with unsupported request status is returned posted writes when the pex 8111 detects pe rr# asserted on the pci prim ary interface while forwarding a non-poisoned posted write transaction fr om pci express, the following occur: pci status register master data parity error bit is set when the pci command register parity error response enable bit is set after the error is detected, the remainder of the data is forwarded 10.2.1.3 pci address errors when the pex 8111 forwards trans actions from pci express-to-pci, pci address errors are reported by serr# assertion by the pci target. the pex 8111 ignores the serr# assertion, and allows the pci central resource function to service the error. 10.2.1.4 pci master abort on posted transaction when a transaction forwarded from pci express-to-pci results in a master abort on the pci bus, the following occur: entire transaction is discarded pci status register received master abort bit is set
june, 2006 reverse bridge pci express originating interface (secondary to primary) pex 8111bb expresslane pci express-to-pci bridge data book 97 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.2.1.5 pci master abor t on non-posted transaction when a non-posted transaction forw arded from pci express-to-pci re sults in a master abort on the pci bus, the following occur: pci express completion with unsupported request status is returned pci status register received master abort bit is set 10.2.1.6 pci target ab ort on posted transaction when a posted transaction forwar ded from pci express-to-pci resu lts in a target abort on the pci bus, the following occur: entire transaction is discarded pci status register received target abort bit is set 10.2.1.7 pci target abor t on non-posted transaction when a non-posted transaction fo rwarded from pci express-to-pci results in a target abort on the pci bus, the following occur: pci express completion with completer abort status is returned pci status register received target abort bit is set 10.2.1.8 pci retry abort on posted transaction when a posted transaction forwarded from pci expres s-to-pci results in a retry abort on the pci bus, the following occur: entire transaction is discarded interrupt re quest status register pci express-to-pci retry interrupt bit is set 10.2.1.9 pci retry abor t on non-posted transaction when a non-posted transaction fo rwarded from pci express-to-pci results in a retry abort on the pci bus, the following occur: pci express completion with completer abort status is returned interrupt re quest status register pci express-to-pci retry interrupt bit is set secondary status register secondary signaled target abort bit is set
error handling plx technology, inc. 98 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.2.2 reverse bridge pc i originating interface (primary to secondary) this section describes error support for transactions that cross the pex 8111 when the originating side is the pci bus, and the destination side is pci express. the pex 8111 supports tlp poisoning as a transmitter, to permit pr oper forwarding of parity errors that occur on the pci interface. posted write data received on the pci interface with bad parity is forwarded to pci express as poisoned tlps. table 10-5 provides the error forwarding requirements for uncorrectable data errors detected by the pex 8111 when a tran saction targets the pci express interface. table 10-6 describes the pex 8111?s behavior on a pci de layed transaction that is forwarded to pci express as a memory read request or an i/o read/w rite request, and the pci express interface returns a completion with ur or ca status for the request. table 10-5. error forwarding requirements received pci error forwarded pci express error write with parity error write request with poisoned tlp read completion with parity error in da ta phase read completi on with poisoned tlp configuration or i/o completion with parity error in data phase read/write completion with completer abort status table 10-6. pex 8111 behavior on a pci delayed transaction pci express completion status pci immediate response master abort mode = 1 master abort mode = 0 unsupported request (on memory read or i/o read) target abort normal completion, return ffff_ffffh unsupported request (on i/o write) target abort normal completion completer abort target abort
june, 2006 reverse bridge pci originating interface (primary to secondary) pex 8111bb expresslane pci express-to-pci bridge data book 99 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.2.2.1 received pci errors uncorrectable data error on non-posted write when a non-posted write is addressed such that it crosses the pex 8111, and the pex 8111 detects an uncorrectable data error on the pc i interface, the following occur: pci status register detected parity error status bit is set. if the pci command register parity error response enable bit is set, the transaction is discarded and is not forwarded to pci express. the pci perr# signal is asserted. if the pci command register parity error response enable bit is not set, the data is forwarded to the pci express interface as a poisoned tlp. the secondary status register secondary master data parity error bit is set when the bridge control register secondary parity error response enable bit is set. the pci perr# signal is not asserted. uncorrectable data error on posted write when the pex 8111 detects an uncorrectable data error on the pci interface for a posted write transaction that crosses the pex 8111, the following occur: pci perr# signal is asserted when the pci command register parity error response enable bit is set pci status register detected parity error status bit is set posted write transaction is forwarded to pci express as a poisoned tlp secondary status register secondary master data parity error bit is set when the bridge control register secondary parity error response enable bit is set uncorrectable data error on pci delayed read completions when the pex 8111 forwards a non-poisoned or pois oned read completion from pci express-to-pci, and perr# is asserted by the pci master, the following occur: remainder of the completion is forwarded pci central resource function services the perr# assertion uncorrectable address error when an uncorrectable address error is detected by the pex 8111 and parity error detection is enabled by way of the pci command register parity error response enable bit, the following occur: transaction is terminated with a target abort pci status register signaled target abort bit is set pci status register detected parity error status bit is set, independent of the setting of the pci command register parity error response enable bit serr# is asserted, when enabled by way of the pci command register serr# enable bit pci status register signaled system error bit is set when serr# is asserted
error handling plx technology, inc. 100 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.2.2.2 unsupported request (ur) completion status the pex 8111 provides two methods for hand ling a pci express co mpletion received with unsupported request (ur) status in response to a re quest originated by the pci interface. the response is controlled by the bridge control register master abort mode bit. in either case, the secondary status register secondary received master abort bit is set. master abort mode bit cleared this is the default pci compatibility mode, and an unsupported request is not considered to be an error. when a read transaction initiated on the pci side of the bridge results in the return of a completion with ur status, the pex 8111 returns ffff_ffffh to the originating master and terminates the read transaction on the orig inating interface normally (by asserting trdy#). when a non-posted write transaction results in a completion with ur status, the pex 8111 completes the write transaction on the originating bus normally (by asserting trdy#) and discards the write data. master abort mode bit set when the bridge control register master abort mode bit is set, the pex 8111 signals a target abort to the originating master of a downstream read or non-posted write transact ion when the corresponding request on the pci express interface results in a completion with ur status. moreover, the pci status register signaled target abort bit is set. 10.2.2.3 completer abort (ca) completion status when the pex 8111 receives a comp letion with completer abort status on the pci express interface in response to forwarded non-po sted pci transactions, the secondary status register secondary received target abort bit is set. a completion with ca status results in a delayed transaction target abort on the pci bus. the pex 8111 provides data to the requesting pci agent, up to the point where data was successfully returned from the pci ex press interface, then sign als target abort. the pci status register signaled target abort status bit is set when signa ling target abort to a pci agent. 10.2.3 reverse bridge timeout errors 10.2.3.1 pci express completion timeout errors the pci express completion timeout mechanism allows requesters to abort a non-posted request when a completion does not arrive within a reasonable length of time. bridges, when acting as initiators on pci express on behalf of internally-generated re quests and requests forwarded from a secondary interface, behave as endpoints for requests that th ey take ownership of. when a completion timeout is detected and the link is up, the pex 8111 responds as when an unsupported request completion is received. when the link is down, the pci control register pci-to-pci express retry count field determines the number of pci retries before a master abort is returned to the pci bus. 10.2.3.2 pci delayed transaction timeout errors the pex 8111 includes delayed transaction time rs for each queued delayed transaction. when a delayed transaction timeout is detected, the following occur: bridge control register discard timer status bit is set delayed request is removed from the non-posted transaction queue serr# is asserted when the pci command register serr# enable bit is set
june, 2006 reverse bridge pci express error messages pex 8111bb expresslane pci express-to-pci bridge data book 101 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 10.2.4 reverse bridge pci express error messages when the pex 8111 detects an err_fatal, err_ nonfatal, or err_cor error, or receives an err_fatal, err_nonfatal, or err_cor message, the pci serr# signal is asserted when the corresponding reporting enable bit in the root control register is set. when an err_fatal or err_nonfatal message is received, the secondary status register secondary received system error bit is set, independent of the reporting enable bits in the root control register. when an unsupported request is received by the pex 8111, an interrupt request status register interrupt status bit is set. this status bit is enabled to generate an int x # or msi interrupt. 10.2.5 reverse bridge ?other? errors pci devices assert serr# when detecting errors that compromise system integrity. the pex 8111 never monitors the serr# ball in reverse bridge mode; instead, it allows the pci central resource function to service the serr# interrupt.
error handling plx technology, inc. 102 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 103 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 11 exclusive (locked) access 11.1 forward bridge exclusive accesses the exclusive access mechanism allows non-exclusive accesses to proceed in the face of exclusive accesses. this allows a master to hold a hardware lock across several accesse s without inte rfering with non-exclusive data transfers. mast ers and targets not involved in the exclusive accesses are allowed to proceed with non-exclusive accesses while another master retains a bus lock. exclusive access support in the pex 8111 is enabled by the pci control register locked transaction enable bit. when this bit is cleared, pci express memory read locked requests are terminated with a completion with ur status. 11.1.1 forward bridge lock sequence across pex 8111 locked transaction sequences are generated by th e host cpu as one or more reads followed by a number of writes to the same locations. in forwar d bridge mode, the pex 8111 supports only locked transactions in the downstream di rection (pci express-to-pci). upst ream locked transactions are not allowed. the initiation of a locked transaction sequence through the pex 8111 is as follows: 1. locked transaction starts with a memory read locked request. 2. successive reads for the locked transactio n also use memory read locked requests. 3. successful memory read locked requests use the cpldlk completion type, cpld. unsuccessful memory read locked requests use the cpllk completion type. (for further details, refer to the pci express base 1.0a , table 2-3.) 4. when the locked completion for the first locked read request is returned, the pex 8111 does not accept new requests from the pci bus. 5. writes for the locked sequence use memory write requests. 6. pex 8111 remains locked until it is unlocked by the pci express interface. unlock is then propagated to the pci bus by te rminating the locked sequence. 7. pci express unlock message is used to indicat e the end of a locked sequence. upon receiving an unlock message, the pex 8111 unlocks itself. wh en the pex 8111 is not locked, it ignores the unlock message. when the locked read request is queued in the pci express-to-pci non-posted transaction queue, subsequent non-posted, non-lock ed requests from the pci express interface are completed with unsupported request status. requests queued before the locked read request are allowed to complete.
exclusive (locked) access plx technology, inc. 104 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 11.1.2 forward bridge pci mast er rules for supporting lock# the pex 8111 must obey the following rules when performing locked sequences on the pci bus: master accesses only a single re source during a lock operation. first transaction of a lo ck operation must be a memory read transaction. lock# must be asserted during the clock cycle fo llowing the address phas e and remain asserted to maintain control. lock# must be released when the initial transaction of the lock request is terminated with retry (lock was not established). lock# must be released when an access is te rminated by target a bort or master abort. lock# must be de-asserted between consecuti ve lock operations for a minimum of one clock cycle while the bus remains in the idle state. 11.1.3 forward bridge acquiring exclusive access across pex 8111 when a pci express locked memory read request appears at the output of the non-posted request queue, the locked request is performed on the pci bus. the pex 8111 monitors the pci lock# ball state when attempting to estab lish lock. when lock# is asserted , the pex 8111 does not request the pci bus to start the transaction. after lock# is de-asserted and the pci bus is id le, req# is asserted. while waiting for gnt#, the pex 8111 continues to monitor lock#. when lock# is busy, the pex 8111 de-asserts req# because another agent gained control of lock#. when the pex 8111 is granted the bus and lock# is not asserted, ownership of lock# is obtained. the pex 8111 is free to perform an exclusive ope ration when the current transaction completes. lock# is de-asserted during the first address phase , and then is asserted one clock cycle later. a locked transaction is not established on the bus un til the first data phase of the first transaction completes (irdy# and trdy# asserted). when the target terminates the firs t transaction with retry, the pex 8111 terminates th e transaction and releases lock#. after the first data phase completes, the pex 8111 holds lock# asserted until the lock operation completes or a master abort or target abort causes an early termination. 11.1.4 forward bridge non-po sted transactions and lock the pex 8111 must consider itself locked when a lo cked memory read request is detected on the output of the non-posted request queue, although no data is transferred. this condition is referred to as a target-lock . while in target-lock, the pex 8111 does not process new requests on pci express. the pex 8111 locks the pci bus when lock sequence on the pci bus completes. a target-lock becomes a full-lock when the locked request is completed on the pci express. at this point, the pci express master established the lock. 11.1.5 forward bridge continuing exclusive access when the pex 8111 performs another transaction to a locked target, lock# is de-asserted during the address phase. the locked target accepts and respond s to the request. lock# is asserted one clock cycle after the address phase to keep the target in the locked state and allow the pex 8111 to retain ownership of lock# beyond the end of the current transaction. 11.1.6 forward bridge completing exclusive access when the pex 8111 receives an un lock message from the pci express, it de-asserts lock# on the pci bus.
june, 2006 forward bridge invalid pci express requests while locked pex 8111bb expresslane pci express-to-pci bridge data book 105 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 11.1.7 forward bridge invalid pci express requests while locked when the pex 8111 is locked, it only accepts pci express memory read lock or memory write transactions that are being forwar ded to the pci bus. other transact ion types are term inated with a completion with unsupported request status, includi ng non-posted accesses to internal configuration registers and shared memory. 11.1.8 forward bridge locked tr ansaction originating on pci bus locked transactions originating on the secondary bus are not allowed to propagate to the primary bus. when a locked transaction is performed on the pc i bus and intended for the pex 8111, the pex 8111 ignores the transaction. 11.1.9 forward bridge pci bus errors while locked 11.1.9.1 pci master abor t during posted transaction when a pci master abort occurs during a pci express-to-pci locked write transaction, the pex 8111 de-asserts lock#, thereby releasi ng the pci bus from the locked stat e. also, the pci express interface is released from the locked state, although no un lock message is received. write data is discarded. refer to section 10.1.1.4, ?pci master abort on posted transaction,? for additional details describing the action taken when a master abort is detected during a posted transaction. 11.1.9.2 pci master abort during non-posted transaction when a pci master abort occurs during a pci express-to-pci locked read transaction, the pex 8111 de-asserts lock#, thereby releasing the pci bus from the locked state. also, the pci express interface is released from the locked state, although no un lock message is received. a cpllk with unsupported request status is returned to the pci express interface. refer to section 10.1.1.5, ?pci master abort on non-posted transaction,? for additional details describing the action taken when a master abor t is detected during a non-posted transaction. 11.1.9.3 pci target abort during posted transaction when a pci target abort occurs during a pci expre ss-to-pci locked write tr ansaction, the pex 8111 de-asserts lock#, thereby releasi ng the pci bus from the locked stat e. also, the pci express interface is released from the locked state, although no un lock message is received. write data is discarded. refer to section 10.1.1.6, ?pci target abort on posted transaction,? for additional details describing the action taken when a target abort is detected during a posted transaction. 11.1.9.4 pci target abort dur ing non-posted transaction when a pci target abort occurs during a pci expres s-to-pci locked read tr ansaction, the pex 8111 de-asserts lock#, thereby releasing the pci bus from the locked state. also, the pci express interface is released from the locked state, although no unlock message is received. a cpllk with completer abort status is returned to the pci express interface. refer to section 10.1.1.7, ?pci target abort on non-posted transaction,? for additional details describing the action taken when a target abor t is detected during a non-posted transaction.
exclusive (locked) access plx technology, inc. 106 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 11.2 reverse bridge exclusive accesses a reverse bridge is allowed to pass locked transact ions from the primary in terface (pci bus) to the secondary interface (pci express interface). when a lo cked request (lock# asserted) is initiated on the pci bus, then a memory read locked request is issued to the pci express interface. all subsequent locked read transactions targeting the pex 811 1 use the memory read locked request on the pci express interface. all subsequent locked write transactions use the memory write request on the pci express interface. the pex 8111 must transmit the unlock mess age when pci lock sequence is complete. exclusive access support in the pex 8111 is enabled by the pci control register locked transaction enable bit. when this bit is cleared, the pci lock# ba ll is ignored, and locked transactions are treated as unlocked transactions. 11.2.1 reverse bridge pci targ et rules for supporting lock# the pex 8111, acting as a target of an access, locks itself when lock# is de-asserted during the address phase and is asserted during the following clock cycle. lock is established when lock# is de-asserted during the address phas e, asserted during the following clock cycle, and data is tr ansferred during the current transaction. after lock is established, the pex 8111 remains locked until both frame# and lock# are sampled de-asserted, regardless of how the transaction is terminated. the pex 8111 is not allowed to accept new requests (from pci or pci express) while it remains in a locked condition, except from the owner of lock#. 11.2.2 reverse bridge acquiring exclusive access across pex 8111 a pci master attempts to forward a locked memory read transaction to the pci express interface. the transaction is terminated by the pex 8111 with a retry, and the locked request is written to the pci-to-pci express non-posted tran saction queue. when this locked request reaches the top of the queue, the locked request is performed on the pci express interface as a memo ry read lock request. when the pci express responds with a locked completion, the locked request is updated with completion status. when the pci master retries the locked memory read request, the pex 8111 responds with trdy#, thereby completing the lock sequence. when the pex 8111 is locked, it only accepts pci locked transactions that are being forwarded to the pci express interface. other bus tr ansactions are terminated with a retry, including accesses to internal configuration registers and shared memory. all pci express requests are terminated with a completion with unsupported request status. 11.2.3 reverse bridge completing exclusive access when the pex 8111 detects lock# and frame# de-ass erted, it transmits an unlock message to the pci express interface. 11.2.4 reverse bridge pci express locked read request when a locked read request is performed on the pci express interface, the pex 8111 responds with a completion with unsupported request status. 11.2.5 reverse bridge limitations in a system with multiple pci mast ers that perform exclusive transact ions to the pci express interface, the pci control register locked transaction enable bit must be set.
pex 8111bb expresslane pci express-to-pci bridge data book 107 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 12 power management 12.1 forward bridge power management pci express defines link power management states, replacing the bus power management states that were defined by the pci power mgmt. r1.1 . link states are not visible to pci power mgmt. r1.1 legacy- compatible software, and are derived from the power management d states or by active state power management protocols. 12.1.1 forward bridge link state power management 12.1.1.1 link power states table 12-1 delineates the link power states supported by the pex 8111 in forward bridge mode. table 12-1. supported link power states (forward bridge mode) link power state description l0 active state. all pci e xpress operations are enabled. l0s a low resume latency, energy-saving ?standby? state. l1 higher latency, lower power ?standby? state. l1 support is required for pci power mgmt. r1.1 -compatible power management. l1 is optional for active state link power management. all platform-provided main power supplies and compone nt reference clocks must remain active at all times in l1. the pex 8111 internal plls are shut off in l1, enabling greater energy savings at a cost of increased exit latency. the l1 state is entered when all functions of a downstream component on a given pci express link are programmed to a d-state other than d0, or when the downstream component requests l1 entry (active state link pm) and re ceives positive acknowledgement for the request. exit from l1 is initiated by an upstream initiated tr ansaction targeting the down stream component, or by the need of the downstream component to initiate a transaction heading upstream. transition from l1 to l0 is typically a few microseconds. tlp and dllp co mmunication over a link that remains in the l1 state is prohibited. the pex 8111 only requests l1 entry for pci power mgmt. r1.1 -compatible power management. when pmein# is asserted, the pex 8111 requests a transition from l1 to l0. l2/l3 ready staging point for removal of main power. l2/l3 rea dy transition protocol support is required. the l2/l3 ready state is related to pci power mgmt. r1.1 d-state transitions. l2/l3 ready is the state that a given link enters into when the platform is preparing to enter its system sleep state. following the completion of the l2/l3 ready state transition protocol for that link, the link is then ready for l2 or l3. depending upon the implementation choices of the platform with respect to providing a vaux supply, after main power is removed, the link settles into l2 ( that is , vaux is provided), or into a zero power ?off? state (refer to l3). the pex 8111 does not support l2; therefore, it settles into the l3 state. the l2/l3 ready state entry transition process must start as soon as possibl e following the pme_to_ack tlp acknowledgment of a pm_turn_off message. the downstream component initiates l2/l3 ready entry by injecting a pm_enter_l23 dllp onto its transmit port. tlp and dllp communication over a link that remains in l2/l3 ready is prohibited. the device exits from l2/l3 ready to l0 when an upstream-initiated tr ansaction targeting the downstream device occurs before main power is re moved and the platform power manager decides not to enter the system sleep state. a link?s transition into the l2/l3 ready state is one of the final stages involving pci express protocol, leading up to the plat form entering into in a system sleep state wherein main power is shut off ( such as , acpi s3 or s4 sleep state). l2 not supported. auxiliary powered link deep energy-saving state. l3 link-off state. power-off state.
power management plx technology, inc. 108 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 12.1.1.2 link state transitions figure 12-1 highlights the l-state transitions which occur during the course of link operations. the arc indicated in the illustration indi cates the case wherein the platfo rm does not provide vaux. link pm transitions from an l-state to a nother l-state pass through the l0 state during the transition process with the exception of the l2/l3 ready to l2 or l3 transitions. in this case, the link transitions from l2/ l3 ready directly to l2 or l3 when main power to the component is removed. (this follows along with a d-state transition from d3, for the corresponding component.) the following sequence, lead ing up to entering a system sleep stat e, illustrates the multi-step link state transition process: 1. system software directs all functions of a downstream co mponent to d3hot. 2. the downstream component then initiates th e transition of the link to l1 as required. 3. system software then causes the root comple x to broadcast the pme_turn_off message in preparation for removing the main power source. 4. this message causes the subject link to transition (return) to l0 to tran smit it, and enable the downstream component to respond with pme_to_ack. 5. after the pme_to_ack is transmitted, the down stream component initiates the l2/l3 ready transition protocol. in summary: l0 ?> l1 ?> l0 ?> l2/l3 ready l2/l3 ready entry sequence is initiated at th e completion of the pme_turn_off/pme_to_ack protocol handshake figure 12-1. l-state transitions during link operations note: in this case, the l2/l3 ready state transition protocol results in a state of readiness for loss of main power, and after removal, the link settles into the l3 state. l0 l0 s l2 l 3 ldn l1 l2/l 3 re a dy l i nk down - tr a n si ent p s e u do- s t a te to get ba ck to l0 - entered thro u gh f u nd a ment a l re s et, hot re s et, or tr a n s m issi on b y the up s tre a m component ret u rn to l0 thro u gh lt ss m l0 s . ft s sub - s t a te l2/l 3 re a dy - p s e u do- s t a te to prep a re component for lo ss of power a nd reference clock( s ) l i nk re i n i t ia l i z a t i on thro u gh lt ss m detect s t a te th is a rc i nd i c a te s the c as e where the pl a tform doe s not prov i de or the dev i ce doe s not us e v au x . in th is c as e, the l2/l 3 re a dy s t a te tr a n si t i on protocol re su lt s i n a s t a te of re a d i ne ss for lo ss of m ai n power, a nd once m ai n power is removed the l i nk s ettle s i nto the l 3 s t a te . ret u rn to l0 thro u gh lt ss m recovery s t a te
june, 2006 forward bridge power management states pex 8111bb expresslane pci express-to-pci bridge data book 109 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 it is also possible to remove power without first placing all devices into d3hot: 1. system software causes the root complex to broadcast the pme_turn_off message in preparation for removing the main power source. 2. the downstream component responds with pme_to_ack. 3. after the pme_to_ack is transmitted, the down stream component initiates the l2/l3 ready transition protocol. in summary: l0 ?> l2/l3 ready 12.1.2 forward bridge power management states the pex 8111 provides the configuration registers and support hardware required by the pci power mgmt. r1.1 . the pci capabilities pointer register points to the base address of the power management registers (offset 40h in the pex 8111). the pex 8111 also supports the pci express active state link power management protocol, as described in section 12.1.1 . 12.1.2.1 power states table 12-2 delineates the power states supported by the pex 8111, selectable by way of the power management control/status register power state field. when transitioning from d0 to another state, the pci expres s link transitions to link state l1. system software must allow a mini mum recovery time following a d3hot-to-d0 transition of at least 10 ms, prior to accessi ng the function. for example , this recovery time is used by the d3hot-to-d0 transitioning component to bootstrap its component interfaces ( such as , from serial rom) prior to being accessible. attempts to target the function during the recovery time (including configuration request packets) results in undefined behavior. table 12-2. supported power states (forward bridge mode) power state description d0_uninitialized power-on default state. this state is ente red when power is initially applied. the pci command register i/o access enable , memory space enable , and bus master enable bits are all cleared to 0. d0_active fully operational. at least one of the following pci command register bits must be set: i/o access enable memory space enable bus master enable d1 light sleep. only pci express configuration transac tions are accepted. other t ypes of transactions are terminated with an unsupported request. all pc i express requests generated by the pex 8111 are disabled except for pme messages. d2 heavy sleep. same restrictions as d1. d3hot function context not maintained. only pci express c onfiguration transactions are accepted. other types of transactions are terminated with an unsupporte d request. all pci express requests generated by the pex 8111 are disabled except for pme messages. from this state, the next power state is d3cold or d0_uninitialized. when transitioning from d3hot-to-d0, the entire pex 8111 is reset. d3cold device is powered-off. a power-on sequence trans itions a function from the d3cold state to the d0_uninitialized state. at this point, software must perform a full initialization of the function to re-establish all functional context, completing the restoration of th e function to its d0_active state.
power management plx technology, inc. 110 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 12.1.3 forward bridge power management signaling pci devices assert pmein# on a pex 8111 ball to signal a power management event (pme). the pex 8111 converts the pmein# signal, received on the pci side of the bridge, to pci express pme messages. there are no internal events th at cause a pme message to transmit upstream. power management messages are used to support power management events signaled by devices downstream of the pex 8111. system software must identify the source of a pci power management event that is reported by a pm_pme message. when the pme comes from an agent on a pci bus, then the pm_pme message requester id reports the bu s number from which the pme was collected, and the device number and function number reported must both be 0. when the pme message is transmitted to the host, the power management control/status register pme status bit is set and a 100 ms timer is started. when the status bit is not cleared within 100 ms, another pme message is transmitted. when the upstream device is powering down the down stream devices, it first places all devices into the d3hot state. it then transmits a pci express pme_turn_off message. after the pex 8111 receives this message, it does not transmit further pme messages upstream. the pex 8111 then transmits a pme_to_ack message to the upstream device and places its link into the l2/l3 ready state. it is now ready to be powered-down. when the upstream device returns the pex 8111 power state to d0, pme messages are re-enabled. the pci express pme_turn_off message terminates at the pex 8111, and is not communicated to the pci devices . the pex 8111 does not issue a pm_pme message on behalf of a downstream pci device while its upstream link remains in the l2/l3 non-communicating state. to avoid loss of pci backplane pme# assertions in the conversion of the level-sensitive pme# signal to the edge-triggered pci express pm_pme message, the pex 8111 polls the pci pmein# ball every 256 ms. a pci express pm_pme message is generated when pmein# is asserted. 12.1.4 set slot power when a pci express link first comes up, or the root complex slot capabilities register slot power limit value or slot power limit scale fields are changed, the root co mplex transmits a set slot power message. when the pex 8111 receives this message, it updates the device capabilities register captured slot power limit value and captured slot power limit scale fields. when the available power indicated by the device capabilities register captured slot power limit va l u e and captured slot power limit scale fields is greater than or equal to the power requirement indicated in the power register, the pwr_ok signal is asserted.
june, 2006 reverse bridge power management pex 8111bb expresslane pci express-to-pci bridge data book 111 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 12.2 reverse bridge power management the pex 8111 supports active state power management (aspm) in reverse bridge mode. the default is that l1 be enabled and l0s be disabled. 12.2.1 reverse bridge active state power management (aspm) 12.2.1.1 aspm states table 12-3 delineates the link power states supported by the pex 8111 in reverse bridge mode. table 12-3. supported link power states (reverse bridge mode) link power state description l0 active state. all pci e xpress operations are enabled. l0s a low-resume latency, energy-saving ?standby? state. when enabled by the serial eeprom or external driver, the pex 8111 transmitter transitions to l0s after a low resume latency, energy-saving ?standby? state. l0s support is required for active state li nk power management. it is not applicable to pci power mgmt. r1.1 -compatible power management. all main powe r supplies, component reference clocks, and components? internal plls must be active at a ll times during l0s. tlp and dllp communication over a link that remains in l0s is prohibited. the l0s state is exclusively used for active-state power management. the pci express physical layer provides mechanisms for quick transitions from this state to the l0 state. when common (distributed) reference clocks are used on both sides of a given link, the transition time from l0s to l0 is typically fewer than 100 symbol times. l1 higher-latency, lower-power ?standby? state. l1 support is required for pci power mgmt. r1.1 -compatible power management. l1 is optional for active state link power management. all platform provided main power supplies and component referenc e clocks must remain active at all times in l1. a component?s internal plls are shut off in l1, enabling greater en ergy savings at a cost of increased exit latency. the l1 state is entered when all functions of a dow nstream component on a given pci express link are programmed to a d-state other than d0, or when th e downstream component requests l1 entry (active state link pm) and receives positive acknowledgement for the request. exit from l1 is initiated by an upstream initiated transaction targeting the downst ream component, or by the downstream component?s need to initiate a transaction head ing upstream. transition from l1 to l0 is typically a few microseconds. tlp and dllp communication over a link that remains in the l1 state is prohibited. l2/l3 ready staging point for removal of main power. l2/l3 rea dy transition protocol support is required. the l2/l3 ready state is related to pci power mgmt. r1.1 d-state transitions. l2/l3 ready is the state that a given link enters into when the platform is preparing to enter its system sleep state. following the completion of the l2/l3 ready state transition protocol for that link, the link is then ready for l2 or l3; the link is not actually in either of those states until main power is removed. if the platform implements a vaux supply voltage, after main power is removed, the link settle s into the l2 state; otherwise, it settles into the l3 state. the pex 8111 does not have vaux capability; however, it supports l2 when the system vaux supply is used as the main power to the pex 8111. the l2/l3 ready state entry transition process must start as soon as possible following pme_to_ack tlp acknowledgment of a pm_turn_off message. the downstream component initiates l2/l3 ready entry by injecting a pm_enter_l23 dllp onto its transmit port. tlp and dllp communi cation over a link that remains in l2/l3 ready is prohibited. the device exits from l2/l3 ready to l0 when an upstream-initiated tr ansaction targeting the downstream device occurs before main power is removed and the platform power manager decides not to enter the system sleep state. a link?s transition into the l2/l3 ready state is one of the final stages involving pci express protocol leading up to the plat form entering into in a system sleep state wherein main power is shut off ( for example , acpi s3 or s4 sleep state). l2 auxiliary-powered link deep energy-saving state. l3 link-off state. power-off state.
power management plx technology, inc. 112 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 12.2.2 reverse bridge power management states the pex 8111 provides the configuration registers and support hardware required by the pci power mgmt. r1.1 . the pci capabilities pointer register points to the ba se address of the power management registers (offset 40h in the pex 8111). 12.2.2.1 power states table 12-4 delineates the power states supported by the pex 8111, selectable by way of the power management control/status register power state field. table 12-4. supported power states (reverse bridge mode) power state description d0_uninitialized power-on default state. this state is entered when power is initially applied . the pci command register i/o access enable , memory space enable , and bus master enable bits are all cleared to 0. d0_active fully operational. at least one of the following pci command register bits must be set: i/o access enable memory space enable bus master enable d1 light sleep. only pci configuration transactions ar e accepted. no master cycles are allowed, and the int x # interrupts are disabled. the pmeout# signal is asserted by the pex 8111 and the pci clock continues to run in this state. d2 heavy sleep. same as d1, except th at the pci host stops the pci clock. d3hot function context not maintained. only pci configurat ion transactions are accepted. from this state, the next power state is d3cold or d0_uninitialized. when transitioning from d3hot-to-d0, the entire pex 8111 is reset. d3cold device is powered-off. a power-on sequence trans itions a function from the d3cold state to the d0_uninitialized state. at this point, software must perform a full initialization of the function to re-establish all functional context, completing the restoration of th e function to its d0_active state.
june, 2006 reverse bridge power down sequence pex 8111bb expresslane pci express-to-pci bridge data book 113 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 12.2.3 reverse bridge power down sequence during a link power-down, the following sequence occurs: 1. pci host places downstream pci express device in d3 power state. 2. downstream device initiates a transition to the l1 link state. 3. pci host places pex 8111 in the d3 power state. 4. pex 8111 initiates a transition to l0 on the link. 5. pex 8111 generates a pci express pme_turn_off message to the pci express downstream device. 6. downstream device responds with a pme_to_ack message. 7. downstream device transmits a dllp to re quest transition to the l2/l3 ready state (l2.idle link state). 8. pex 8111 acknowledges the request, completing the transition to th e l2.idle link state. 9. pmeout# signal is asserted to the pci host. 10. pci host can now remove power from the pex 8111. 12.2.4 reverse bridge pmeout# signal pme messages from the pci express interface are tr anslated to the pci bac kplane pmeout# signal on the pex 8111. the power management control/status register pme status bit is set when a pci express pme message is received, the wakein# signal is asserted, a beacon is detected, or the link transitions to the l2/l3 ready stat e. pmeout# is asserted when the pme status bit is set and pme is enabled. 12.2.5 reverse bridge set slot power when a pci express link firs t comes up, or the pex 8111 slot capabilities register slot power limit va l u e or slot power limit scale fields are changed, the pex 8111 tr ansmits a set slot power message to the downstream pci express device. when the downstream device receives this message, it updates the device capabilities register captured slot power limit value and captured slot power limit scale fields.
power management plx technology, inc. 114 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 115 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 13 pci express messages 13.1 forward bridge pci express messages pci express defines a set of messages that are used as a method for in-band communication of events ( such as interrupts), generally replacing the need for si deband signals. these messages are also used for general-purpose messaging. pci express-to-pci bri dge support requirements for these messages are described in the following sections. pci express messages are routed explicitly or implicitly depending on specific bit field encodings in the message request header. an explicit ly routed message is routed base d on a specific address or on an id field contained within the message header. the destin ation of an implicitly routed message is inferred from the message type field. 13.1.1 forward bridge int x # interrupt signaling int x # interrupt signaling messages are used for in -band communication of the state of the pci line-based interrupts inta#, intb#, intc#, and intd# for downstream devices. (refer to section 5.1, ?forward bridge pci interrupts,? for details.) 13.1.2 forward bridge power management messages power management messages are used to suppor t power management events signaled by sources integrated into the pex 8111 and fo r downstream devices. (refer to section 12.1, ?forward bridge power management,? for details.) 13.1.3 forward bridge error signaling messages error signaling messages are transmitted by the pex 8111 on its pci express primary interface, to signal errors for any of the following: a particular transaction the link interface errors internal to the pex 8111 pci-related errors detected on the secondary interface the message types include err_cor, err_fatal, and err_nonfatal. the relevant mask bits are located in the pci express ca pability structure. (refer to section 10.1, ?forward bridge error handling,? for details.)
pci express messages plx technology, inc. 116 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 13.1.4 forward bridge lock ed transactions support the pci express unlock message is used to suppor t locked transaction sequences in the downstream direction. (refer to section 11.1, ?forward br idge exclusive accesses,? for details.) 13.1.5 forward bridge slot power limit support the set slot power limit message is transmitted to endpoints, including bridges, by the root complex or a switch. the pex 8111 supports and complies w ith these messages. these messages are particularly relevant to bridges implemented on add-in boards. (refer to section 12.1, ?forward bridge power management,? for details.) 13.1.6 forward bridge ho t plug signaling messages the pex 8111 does not support hot plug signaling, and igno res the associated messages.
june, 2006 reverse bridge pci express messages pex 8111bb expresslane pci express-to-pci bridge data book 117 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 13.2 reverse bridge pci express messages 13.2.1 reverse bridge int x # interrupt message support the pex 8111 controls the state of the corresponding pci interrupt pins based on the assert_int x and deassert_int x messages received. 13.2.2 reverse bridge power management message support the pex 8111 generates a pme_turn_off message when placed into power state d3. the pex 8111 then waits for the pme_to_ack message from th e downstream device before proceeding with the power-down sequence. 13.2.2.1 pme handl ing requirements the pex 8111 translates pme messages from the pci express interface to the pci backplane pme# signal. the pex 8111 converts the edge-triggered pmes on the pci express interface to the level-triggered pme# signal on the pci bus. the pex 8111 signals pmeout# on the pci bus for the following: pci express wakein# signal is asserted while the link is in the l2 state pci express beacon is received while the link is in the l2 state pci express pm_pme message is received for compatibility with existing software, the pex 8111 does not signal pmeout# unless the pme signaling is enabled by the power management control/status register pme enable bit. the pex 8111 sets the power management control/status register pme status bit when pmeout# is signaled and de-asserts pmeout# when the pme enable or pme status bit is cleared. all pme messages received while the pme enable bit is cleared are ignored and the pme status bit is not set during this time. 13.2.3 reverse bridge error signaling message support the pex 8111 converts all err_cor, err_fatal, and err_nonfatal messages to serr# on the pci interface. 13.2.4 reverse bridge locked transaction support the pex 8111 is allowed to pass locked transact ions from the primary interface to the secondary interface. the pex 8111 uses the memory read locked request to initiate a locked sequence when a locked request is transmitted on th e pci bus. all subsequent locked read transactions targeting the pex 8111 use the memory read locked request on th e pci express interface. all subsequent locked write transactions use the memory write request on the pci expres s interface. the pex 8111 transmits the unlock message when the pci lock sequence is complete. (refer to section 11.2, ?reverse bridge exclusive accesses,? for details.) 13.2.5 reverse bridge slot power limit support the set slot power limit message is transmitted to endpoints, including bridges, by the root complex or a switch. the pex 8111 supports and complies w ith these messages. these messages are particularly relevant to bridges implemente d on add-in boards. (refer to section 12.2, ?reverse bridge power management,? for details.)
pci express messages plx technology, inc. 118 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 119 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 14 pci arbiter 14.1 overview a pci system using the pex 8111 utilizes an external bus arbiter, or the pex 8111 internal arbiter. this internal arbiter accepts bus requests from up to four external pci devices. the pci express-to-pci bridge controller logic also requests control of the pci bus. 14.2 internal arbiter mode when the extarb signal is de-asserted, the pex 8111 accepts and arbitrates pci requests from up to four external devices. the pex 8111 supports single and multi-level arbiter modes, selected by the pci control register pci multi-level arbiter bit. 14.2.1 single-level mode the four external requests and the pci express-to-p ci bridge controller request are placed into a single-level arbiter. after a device is granted the bu s, it becomes the lowest level requester. all devices have the same priority. for example , when all internal and external ag ents are requesting the bus, then the order of the agents granted the bus would be: pex 8111 pci initiator external requester 0 external requester 1 external requester 2 external requester 3 bridge and so forth. 14.2.2 multi-level mode the four external requests are placed into a two- level round robin arbiter with the pci express-to-pci bridge controller. level 0 alternates between the pci express-to-pci bridge controller and level 1, guaranteeing that the pci express-to -pci bridge is granted up to 50 % of the accesses. level 1 consists of the four external pci requesters. for example , when all internal and external agents are re questing the bus, then the order of the agents that are granted the bus would be: pex 8111 pci initiator external requester 0 pex 8111 pci initiator external requester 1 pex 8111 pci initiator external requester 2 pex 8111 pci initiator external requester 3 and so forth.
pci arbiter plx technology, inc. 120 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 14.3 external arbiter mode when the extarb signal is asserted, the pex 8111 pci request inputs to the internal arbiter are disabled. the pex 8111 generates a pci request (req0#) to an external arbiter when it must use the pci bus. the pci grant input (gnt0#) to the pex 8111 allows it to become the pci bus master. 14.4 arbitration parking the pci bus is not allowed to float for more than ei ght clock cycles. when ther e are no requests for the bus, the arbiter selects a device to drive the bus to a known state, by driving its gnt# ball active. when the extarb signal is de-asserted (internal arbite r mode), the pex 8111 selects a pci master to be parked on the bus during idle periods. the pci control register pci arbiter park select field determines which master is parked on the bus. when parked (gnt# driven during idle bus), the pex 8111 drives ad[31:0], cbe[3:0]#, and par to a known state. the pex 8111 drives ad[31:0], cbe[3:0]#, and par with the previous output value. in forward bridge mode, the pex 8111 parks on the pci bus during reset, independent of the extarb signal, and drives ad[31:0], cbe[3:0]#, and par low.
pex 8111bb expresslane pci express-to-pci bridge data book 121 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 15 forward bridge mode configuration registers 15.1 register description this chapter describes the pex 8111 configuration registers specific to forward bridge mode. registers specific to reverse br idge mode are discussed in chapter 16 . the pci-compatible forward bridge mode confi guration registers are acce ssed by the pci express root complex, using the pci co nfiguration address space. all c onfiguration registers are accessed from the pci express interface or pci bus, using the 64-kb memory space defined by the pci base address 0 register. registers that are written by the se rial eeprom controller are also written using memory writes through the pci base address 0 register. when the configuration regi sters are accessed using memo ry transactions to the pci base address 0 register, the register map delineated in table 15-1 is used. the serial eeprom controller writes to configuration registers. an upper address bit is used to select one of two register spaces, as delineated in table 15-2 . each register is 32 bits wide, and is accessed on e byte, word, or dword at a time. these registers utilize little endian byte ordering, which is consistent with the pci r3.0 . the least significant byte in a dword is accessed at address 0. the least significant bit in a dword is 0, and the most significant bit is 31. after the pex 8111 is powered up or reset, the registers are set to their default values. writes to unused registers are ignored, and reads from unused registers return a value of 0. 15.1.1 indexed addressing in addition to me mory-mapped accesses, the pex 8111 main configuration registers can be accessed using the main control register index and main control register data registers. this method allows all main configuration registers to be acces sed using configuration tr ansactions, rather than memory transactions. first, the main configuration register offset is written to the main control register index register (offset 84h). then, the main configuration register is written or read by accessing the main control register data register (offset 88h). table 15-1. forward bridge mode pci base address 0 register map address offset register space 0000h - 0fffh pci-compatible configuration registers 1000h - 1fffh main configuration registers 2000h - 2fffh ? 8000h - 9fffh 8-kb internal shared memory table 15-2. selecting register space ad12 register space 0 pci-compatible configuration registers 1 main configuration registers
forward bridge mode configuration registers plx technology, inc. 122 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.2 configuration access types table 15-3 delineates configuration acce ss types referenced by the registers in this chapter. 15.3 register attributes table 15-4 delineates the register attributes used to in dicate access types provided by each register bit. table 15-3. configuration access types access type description cfg initiated by pci configuration transactions on the primary bus. mm initiated by pci memory transactions on the primary or secondary bus, using the address range defined by the pci base address 0 register. ee initiated by the serial eeprom controller during initialization. table 15-4. access provided by register bits register attribute description hwinit hardware initialized register bits are initialized by firmware or hardware mechanisms such a s ball strapping (on the bar0enb# , extarb , and forward balls) or serial eeprom. bits are read-only after initialization and re set only with ?fundamental reset.? ro read-only register register bits are read-only and cannot be altered by software. register bits are initialized by a pex 8111 hardware initia lization mechanism or pex 811 1 serial eeprom register initialization feature. rsvdp reserved and preserved reserved for future rw implementations. register s are read-only and must return 0 when read. software must preserve value read for writes to bits. rsvdz reserved and zero reserved for future rw1c implementations. regi sters are read-only and must return 0 when read. software must use 0 for writes to bits. rw read-write register register bits are read-write and set or cleared by software to the needed state. rw1c read-only status, write 1 to clear status register register bits indicate status when read; a set bit indicating a status event is cleared by writing 1. writing 0 to rw1c bits has no effect. wo write-only used to indicate that a register is written by the serial eeprom controller.
june, 2006 register summary pex 8111bb expresslane pci express-to-pci bridge data book 123 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.4 register summary table 15-5. forward bridge mode register summary register group pci space address range pci-compatible configuration registers (type 1) pci express configuration 00h - 0ffh memory-mapped, bar0 pci express extended capability registers pci express configuration 100h - 1ffh memory-mapped, bar0 main control registers memory-mapped, bar0 1000h - 10ffh pci express configuration registers using enhanced configuration access memory-mapped, bar0 2000h - 2fffh 8-kb shared memory instead of general pu rpose memory memory-mapped, bar0 8000h - 9fffh
forward bridge mode configuration registers plx technology, inc. 124 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.5 register maps 15.5.1 pci-compatible configuration registers (type 1) table 15-6. forward bridge mode pci-compatible configuration (type 1) register map pci configuration register offset 31 24 23 16 15 8 70 00h pci device id pci vendor id 04h pci status pci command 08h pci class code pci device revision id 0ch pci built-in self-test (not supported) pci header type pci bus latency timer pci cache line size 10h pci base address 0 14h pci base address 1 18h secondary latency timer subordinate bus number secondary bus number primary bus number 1ch secondary status i/ o limit i/o base 20h memory limit memory base 24h prefetchable memory limit prefetchable memory base 28h prefetchable memory base upper 32 bits 2ch prefetchable memory limit upper 32 bits 30h i/o limit upper 16 bits i/ o base upper 16 bits 34h reserved pci capabilities pointer 38h pci base address for expansion rom ( not supported ) 3ch bridge control pci interrupt pin pci interrupt line
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 125 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.5.2 pci-compatible exte nded capability registers for pci express interface table 15-7. forward bridge mode pci-compatible extended capability for pci express interface register map pci configuration register offset 31 24 23 16 15 8 70 40h power management capabilities power management next capability pointer power management capability id 44h power management data power management bridge support power management control/status 48h device-specific control 4ch reserved 50h message signaled interrupts control message signaled interrupts next capability pointer message signaled interrupts capability id 54h message signaled in terrupts address 58h message signaled inte rrupts upper address 5ch reserved message signaled interrupts data 60h pci express capabilities pci express next capability pointer pci express capability id 64h device ca pabilities 68h pci express device status pci express device control 6ch link capabilities 70h link status link control 74h slot capabilities 78h slot status slot control 7ch - 80h reserved 84h main control register index 88h main control register data
forward bridge mode configuration registers plx technology, inc. 126 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.5.3 pci express extend ed capability registers table 15-8. forward bridge mode power budgeting capability and device serial number register map pci express configuration register offset 31 20 19 16 15 8 70 100h power budgeting next capability offset power budgeting capability ve r s i o n power budgeting pci express extended capability id 104h reserved power budgeting data select 108h power budgeting data 10ch reserved power budget capability 110h serial number next capability offset serial number capability ve r s i o n serial number pci express extended capability id 114h serial number low (lower dword) 118h serial number hi (upper dword)
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 127 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.5.4 main control registers table 15-9. forward bridge mode 32-bit main control register map pci express configuration register offset 31 0 1000h device initialization 1004h serial eeprom control 1008h serial eeprom clock frequency 100ch pci control 1010h pci express interrupt request enable 1014h reserved 1018h interrupt request status 101ch power 1020h general-purpose i/o control 1024h general-purpose i/o status 1030h mailbox 0 1034h mailbox 1 1038h mailbox 2 103ch mailbox 3 1040h chip silicon revision 1044h diagnostic control (factory test only) 1048h tlp controller configuration 0 104ch tlp controller configuration 1 1050h tlp controller configuration 2 1054h tlp controller tag 1058h tlp controller time limit 0 105ch tlp controller time limit 1 1060h crs timer 1064h enhanced configuration address
forward bridge mode configuration registers plx technology, inc. 128 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.6 pci-compatible configur ation registers (type 1) register 15-1. (offset 00h; pcivendid) pci vendor id bit(s) description cfg mm ee default 15:0 pci vendor id identifies the pex 8111 manufacturer. the pex 8111 returns the plx pci-sig-assigned vendor id, 10b5h. ro rw wo 10b5h register 15-2. (offset 02h; pcidevid) pci device id bit(s) description cfg mm ee default 15:0 pci device id identifies the particular device, as specified by the vendor. the pex 8111 returns the plx-assigned device id, 8111h. ro rw wo 8111h
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 129 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-3. (offset 04h; pcicmd) pci command bit(s) description cfg mm ee default 0 i/o access enable enables the pex 8111 to respond to i/o space accesses on the primary interface (pci express). these accesses must be directed to a target on the pci bus, because the pex 8111 does not have inte rnal i/o-mapped resources. 0 = pex 8111 responds to all i/o reques ts on its primary interface with an unsupported request completion rw rw wo 0 1 memory space enable enables the pex 8111 to respond to memory space accesses on the primary interface (pci express). these accesses are directed to a target on the pci bus, or to intern al memory-mapped registers. 0 = pex 8111 responds to all memory requests on the primary interface with an unsupported request completion rw rw wo 0 2 bus master enable enables the pex 8111 to issue memo ry and i/o read/write requests on the primary interface (pci express). requests other than memory or i/o requests are not controlled by this bit. 0 = pex 8111 does not respond (issue a target abort) to memory nor i/o transactions on the pci bus secondary interface. no memory or i/o transactions are forwarded to the pci express primary interface. rw rw wo 0 3 special cycle enable does not apply to pci express; therefore, forced to 0. ro ro ? 0 4 memory write and invalidate 0 = enables the pex 8111 pci bus master logic to use the memory write command 1 = enables the pex 8111 pci bus master logic to use the memory write and invalidate command rw rw wo 0 5 vga palette snoop does not apply to pci express; therefore, forced to 0. ro ro ? 0 6 parity error response enable controls the pex 8111?s response to data parity errors forwarded from the primary interface ( such as , a poisoned tlp). 0 = pex 8111 must ignore (but records status such as setting the pci status register detected parity error bit) data parity errors detected and continue standard operation 1 = pex 8111 must take its standard action when a data parity error is detected rw rw wo 0 7 address stepping enable the pex 8111 performs address steppi ng for pci configuration cycles; therefore this bit is read/write with an initial value of 1. rw rw wo 1
forward bridge mode configuration registers plx technology, inc. 130 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8 serr# enable enables reporting of fatal and non-fa tal errors to the root complex. note: errors are reported when enabl ed through this bit or through the pci express device control register pci expr ess-specific bits. rw rw wo 0 9 fast back-to-back enable does not apply to pci express; therefore, forced to 0. ro ro ? 0 10 interrupt disable when set: pex 8111 is prevented from generating int x # interrupt messages on behalf of functions integrated into the pex 8111 int x # emulation interrupts previously asserted must be de-asserted there is no effect on int x # messages generated on behalf of int x # inputs associated with the pci bus secondary interface. rw rw wo 0 15:11 reserved rsvdp rsvdp ? 0h register 15-3. (offset 04h; pcicmd) pci command (cont.) bit(s) description cfg mm ee default
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 131 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-4. (offset 06h; pcistat) pci status bit(s) description cfg mm ee default 2:0 reserved rsvdz rsvdz ? 000b 3 interrupt status 1 = indicates that an int x # interrupt message is pending on behalf of functions integrated into the pex 8111 does not reflect the status of int x # inputs associated with the secondary interface. ro ro ? 0 4 capabilities list indicates whether the pci capabilities pointer at offset 34h is valid. because all pci express devices are required to implement the pci express capability structure, this bit is hardwired to 1. ro ro ? 1 5 66-mhz capable does not apply to pci express; therefore, forced to 0. ro ro ? 0 6 reserved rsvdz rsvdz ? 0 7 fast back-to-back transactions capable does not apply to pci express; therefore, forced to 0. ro ro ? 0 8 master data parity error used to report data parity error de tection by the pex 8111. set when the pci command register parity error response enable bit is set and either of the following two conditions occur: bridge receives a completion mark ed poisoned on primary interface bridge poisons a write request or read completion on primary interface writing 1 clears this bit. rw1c rw1c ? 0 10:9 devsel timing does not apply to pci express; therefore, forced to 0. ro ro ? 00b 11 signaled target abort set when the pex 8111 completes a reque st as a transaction target on its primary interface using completer abor t completion status. writing 1 clears this bit. rw1c rw1c ? 0 12 received target abort set when the pex 8111 receives a completion with completer abort completion status on its primary interface. writing 1 clears this bit. rw1c rw1c ? 0 13 received master abort set when the pex 8111 receives a co mpletion with unsupported request completion status on its primary interface. writing 1 clears this bit. rw1c rw1c ? 0 14 signaled system error set when the pex 8111 transmits an err_fatal or err_nonfatal message to the root complex, and the pci command register serr# enable bit is set. writing 1 clears this bit. rw1c rw1c ? 0 15 detected parity error set when the pex 8111 receives a pois oned tlp on the primary interface, regardless of the pci command register parity error response enable bit state. writing 1 clears this bit. rw1c rw1c ? 0
forward bridge mode configuration registers plx technology, inc. 132 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-5. (offset 08h; pcidevrev) pci device revision id bit(s) description cfg mm ee default 7:0 pci device revision id identifies the pex 8111 silicon revision. bi ts [3:0] represent the minor revision number and bits [7:4] repres ent the major revision number. ro ro ? 21h register 15-6. (offset 09h; pciclass) pci class code bit(s) description cfg mm ee default 7:0 programming interface ro rw wo 00h 15:8 subclass code ro rw wo 04h 23:16 base class code ro rw wo 06h register 15-7. (offset 0ch; pcicachesize) pci cache line size bit(s) description cfg mm ee default 7:0 pci cache line size specifies the system cache line size (in units of dwords). the value in this register is used by pci master devices to determine whether to use read, memory read line, memory read multiple, or memory write and invalidate commands for accessing memory. the pex 8111 supports cache li ne sizes of 2, 4, 8, 16, or 32 dwords. writes of values other than these result in a cach e line size of 0; however, the value written is returned when this register is read. rw rw wo 0h register 15-8. (offset 0dh; pcilatency) pci bus latency timer bit(s) description cfg mm ee default 7:0 pci bus latency timer also referred to as primary latency timer for type 1 configuration space header devices. the primary/master latency time r does not apply to pci express. ro ro ? 0h register 15-9. (offset 0eh; pciheader) pci header type bit(s) description cfg mm ee default 7:0 pci header type specifies the format of the second part of the pre-defined configuration header starting at offset 10h. for pci bri dges, this field is forced to 1h. ro ro ? 1h
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 133 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-10. (offset 0fh; pcibist) pci built-in self-test bit(s) description cfg mm ee default 7:0 pci built-in self-test not supported . always returns a value of 0h. ro ro ? 0h register 15-11. (offset 10h; pcibase0) pci base address 0 bit(s) description cfg mm ee default 0 space type when low, this space is accessed as memory. when high, this space is accessed as i/o. note: hardwired to 0. ro ro ? 0 2:1 address type indicates the type of a ddressing for this space. 00b = locate anywhere in 32-bit address space 01b = locate below 1 mb 10b = locate anywhere in 64-bit address space 11b = reserved ro rw wo 10b 3 prefetch enable 1 = indicates that prefetchi ng has no side effects on reads ro rw wo 1 15:4 base address this section of the base addre ss is ignored for a 64-kb space. note: hardwired to 0. ro ro ? 0h 31:16 base address specifies the upper 16 bits of the 32-bi t starting base address of the 64-kb address space for the pex 8111 configur ation registers and shared memory. rw rw wo 0h register 15-12. (offset 14h; pcibase1) pci base address 1 bit(s) description cfg mm ee default 31:0 base address 1 determines the upper 32 bits of the address when pci base address 0 is configured for 64-bit addressing. rw rw wo 0h
forward bridge mode configuration registers plx technology, inc. 134 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-13. (offset 18h; primbusnum) primary bus number bit(s) description cfg mm ee default 7:0 primary bus number used to record the bus number of th e pci bus segment to which the primary interface of the pex 8111 is connected. rw rw wo 0h register 15-14. (offset 19h; secbusnum) secondary bus number bit(s) description cfg mm ee default 7:0 secondary bus number used to record the bus number of the pci bus segment to which the pex 8111 secondary interfac e is connected. rw rw wo 0h register 15-15. (offset 1ah; subbusnum) subordinate bus number bit(s) description cfg mm ee default 7:0 subordinate bus number used to record the bus number of the highest-numbered pci bus segment behind (or subordinate to) the pex 8111. rw rw wo 0h register 15-16. (offset 1bh; seclattimer) secondary latency timer bit(s) description cfg mm ee default 7:0 secondary latency timer specifies (in pci clock uni ts) the latency timer valu e during secondary (pci) bus master bursts. when the latenc y timer expires, the pex 8111 must terminate its tenure on the bus. rw rw wo 0h
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 135 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-17. (offset 1ch; iobase) i/o base bit(s) description cfg mm ee default 3:0 i/o base address capability indicates the type of a ddressing for this space. 0000b = 16-bit i/o address 0001b = 32-bit i/o address all other values are reserved . ro rw wo 0000b 7:4 i/o base determines the starting address at wh ich i/o transactions on the primary interface are forwarded to the secondary interface. the upper four bits of this register correspond to address bits ad[ 15:12]. for address decoding purposes, the pex 8111 assumes that the lower 12 a ddress bits, ad[11:0], of the i/o base address are zero (0h). therefore, the bottom of the defined i/o address range is aligned to a 4-kb address boundary sp ace, and the top is one less than a 4-kb address boundary space. rw rw wo 0h register 15-18. (offset 1dh; iolimit) i/o limit bit(s) description cfg mm ee default 3:0 i/o limit address capability indicates the type of addressing for this space. 0000b = 16-bit i/o address 0001b = 32-bit i/o address all other values are reserved . the value returned in this field is derived from the i/o base register i/o base address capability field. ro ro ? 0000b 7:4 i/o limit determines the i/o space range forwar ded from the primary interface to the secondary interface. the upper four bits of this register correspond to address bits ad[15:12]. for address decoding purposes, the pex 8111 assumes that the lower 12 address bits, ad[11:0], of the i/o limit address are fffh. when there are no i/o addresses on the secondary side of the bridge, the i/o limit field is programmed to a value smaller than the i/o base register i/o base field. in this case, the pex 8111 does not forward i/o transactions from the primary bus to the secondary bus; however, the pex 8111 does forward all i/o transactions from the seconda ry bus to the primary bus. rw rw wo 0h
forward bridge mode configuration registers plx technology, inc. 136 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-19. (offset 1eh; secstat) secondary status bit(s) description cfg mm ee default 4:0 reserved rsvdz rsvdz ? 0h 5 secondary 66-mhz capable indicates whether the pex 8111 secondary interface is capable of operating at 66 mhz. ro ro ? 0 6 reserved rsvdz rsvdz ? 0 7 secondary fast back-to-back transactions capable indicates whether the pex 8111 secondary interface is ca pable of decoding fast back-to-back transactions when the transactions are from the same master but to different targ ets. (a bridge is requir ed to support fast back-to- back transactions from the same master.) the pex 8111 does not support fast back-to-back decoding. ro ro ? 0 8 secondary master data parity error reports data parity error detection by the pex 8111 when it is the master of the transaction on the secondary interf ace. set when the following three conditions are true: bridge is the bus master of the transaction on sec ondary interface bridge asserted perr# (read transact ion) or detected perr# asserted (write transaction) bridge control register secondary parity error response enable bit is set writing 1 clears this bit. rw1c rw1c ? 0 10:9 secondary devsel timing encodes the secondary interface de vsel# timing. the encoding must indicate the slowest response time that the pex 8111 uses to assert devsel# on its secondary interface when respondi ng as a target to a transaction other than a configuration read or write. 01b = indicates medium devsel# timing note: hardwired to 01b. ro ro ? 01b 11 secondary signaled target abort reports target abort termination si gnaling by the pex 8111 when it responds as the transaction target on its secondary interface. wr iting 1 clears this bit. rw1c rw1c ? 0
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 137 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 12 secondary received target abort reports target abort termination dete ction by the pex 8111 when it is the transaction master on its secondary interface. writing 1 clears this bit. rw1c rw1c ? 0 13 secondary received master abort reports master abort termination dete ction by the pex 8111 when it is the transaction master on its secondary interface. also set for a pci express-to- pci configuration transaction with an extended address not equal to 0. writing 1 clears this bit. rw1c rw1c ? 0 14 secondary received system error reports serr# assertion detection on the pex 811 1 secondary interface. writing 1 clears this bit. rw1c rw1c ? 0 15 secondary detected parity error reports address or data parity e rror detection by the pex 8111 on its secondary interface. set when any of the following three conditions are true: bridge detects an address pari ty error as a potential target bridge detects a data parity error when a write transaction target bridge detects a data parity error when a read transaction master set irrespective of the bridge control register secondary parity error response enable bit state. writing 1 clears this bit. rw1c rw1c ? 0 register 15-19. (offset 1eh; secstat) secondary status (cont.) bit(s) description cfg mm ee default
forward bridge mode configuration registers plx technology, inc. 138 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-20. (offset 20h; membase) memory base bit(s) description cfg mm ee default 3:0 reserved note: hardwired to 0h. rsvdp rsvdp ? 0h 15:4 memory base determines the starting address at whic h memory transactions on the primary interface are forwarded to the secondar y interface. the upper 12 bits of this register correspond to address bits ad[ 31:20]. for address decoding purposes, the pex 8111 assumes that the lower 20 address bits, ad[19:0], of the memory base address are zero (0h). the bottom of the defined memory addre ss range is aligned to a 1-mb address boundary space, and the top is one less than a 1-mb address boundary space. rw rw wo ? register 15-21. (offset 22h; memlimit) memory limit bit(s) description cfg mm ee default 3:0 reserved note: hardwired to 0h. rsvdp rsvdp ? 0h 15:4 memory limit determines the memory space range fo rwarded from the primary interface to the secondary interface. the upper 12 bits of this register correspond to address bits ad[31:20]. for addr ess decoding purposes, the pex 8111 assumes that the lower 20 address bi ts, ad[19:0], of the memory limit address are fffffh. when there are no memory-mapped i/o a ddresses on the secondary side of the bridge, the memory limit field must be programmed to a value smaller than the memory base register memory base field. when there is no prefetchable memo ry, and no memory-mapped i/o on the secondary side of the bridge, th e pex 8111 does not forward memory transactions from the primary bus to the secondary bus; however, it does forward all memory transactions from the secondary bus to the primary bus. rw rw wo ?
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 139 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-22. (offset 24h; prebase) prefetchable memory base bit(s) description cfg mm ee default 3:0 prefetchable base address capability indicates the type of addressing for this space. 0000b = 32-bit i/o address 0001b = 64-bit i/o address all other values are reserved . ro rw wo 0000b 15:4 prefetchable memory base determines the starting address at which prefetchable memory transactions on the primary interface are forwarded to th e secondary interface. the upper 12 bits of this register correspond to address bits ad[31:20]. for address decoding purposes, the pex 8111 assumes that the lower 20 address bits, ad[19:0], of the prefetchable memory base address are zero (0h). the bottom of the defined prefetchable memory address range is aligned to a 1-mb address boundary space, and the top is one less than a 1-mb address boundary space. rw rw wo ? register 15-23. (offset 26h; prelimit) prefetchable memory limit bit(s) description cfg mm ee default 3:0 prefetchable limit address capability indicates the type of addressing for this space. 0000b = 32-bit i/o address 0001b = 64-bit i/o address all other values are reserved . the value returned in this field is derived from the prefetchable memory base register prefetchable base address capability field. ro ro ? 0000b 15:4 prefetchable memory limit determines the prefetchable memory space range forwarded from the primary interface to the secondary interface. the up per 12 bits of this register correspond to address bits ad[31:20]. for a ddress decoding purposes, the pex 8111 assumes that the lower 20 address bits, ad[19:0], of the prefetchable memory limit address are fffffh. when there is no prefetchable memory on the secondary side of the bridge, the prefetchable memory limit field must be programmed to a value smaller than the prefetchable memory base register prefetchable memory base field. when there is no prefetchable memory, and no memory-mapped i/o on the secondary side of the bridge, th e pex 8111 does not forward memory transactions from the primary bus to the secondary bus; however, it does forward all memory transactions from the secondary bus to the primary bus. rw rw wo ?
forward bridge mode configuration registers plx technology, inc. 140 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-24. (offset 28h; prebaseupper) prefetchable memory base upper 32 bits bit(s) description cfg mm ee default 31:0 prefetchable memory base upper 32 bits when the prefetchable memory base register prefetchable base address capability field indicates 32-bit addressing, this register is read-only and returns 0h. when the prefetchable base address capability field indicates 64-bit addressing, this register determines the upper 32 bits of the starting address at which prefetchable memory transactions on the primary interface are forwarded to the secondary interface. rw rw wo 0h register 15-25. (offset 2ch; prelimitupper) prefetchable memory limit upper 32 bits bit(s) description cfg mm ee default 31:0 prefetchable memory limit upper 32 bits when the prefetchable memory limit register prefetchable limit address capability field indicates 32-bit a ddressing, this regist er is read-only and returns 0h. when the prefetchable limit address capability field indicates 64-bit addressing, this register determines the upper 32 b its of the prefetchable memory range forwarded from the primary interf ace to the secondary interface. rw rw wo 0h register 15-26. (offset 30h; iobaseupper) i/o base upper 16 bits bit(s) description cfg mm ee default 15:0 i/o base upper 16 bits when the i/o base register i/o base address capability field indicates 16-bit addressing, this register is read-only and returns 0h. when the i/o base addr ess capability field indicates 32-bi t addressing, this register determines the upper 16 bits of the starting address at which i/o transactions on the primary interface ar e forwarded to the secondary interface. rw rw wo ? register 15-27. (offset 32h; ioli mitupper) i/o limit upper 16 bits bit(s) description cfg mm ee default 15:0 i/o limit upper 16 bits when the i/o limit register i/o limit address capability field indicates 16-bit addressing, this register is read-only and returns 0h. when the i/o limit address capability field indicates 32-bit addressing, this register determines the upper 16 bits of the i/o range forwarded from the primary interface to the secondary interface. rw rw wo ?
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 141 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-28. (offset 34h; pcicapptr) pci capabilities pointer bit(s) description cfg mm ee default 7:0 pci capabilities pointer provides the offset location of the first new capabilities register. ro rw wo 40h 31:8 reserved rsvdp rsvdp ? 0h register 15-29. (offset 3ch; pciintline) pci interrupt line bit(s) description cfg mm ee default 7:0 pci interrupt line indicates to which system interrupt cont roller input the pex 8111 interrupt ball is connected. device drivers and operating systems use this field. rw rw wo 0h register 15-30. (offset 3dh; pciintpin) pci interrupt pin bit(s) description cfg mm ee default 7:0 pci interrupt pin identifies the legacy interrupt message( s) used by the pex 8111. valid values are 1, 2, 3, and 4, which map to legacy interrupt messages for inta#, intb#, intc#, and intd#, respectively. 0h = indicates that the pex 8111 does not use legacy interrupt messages ro rw wo 1h
forward bridge mode configuration registers plx technology, inc. 142 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-31. (offset 3eh; bridgectl) bridge control bit(s) description cfg mm ee default 0 secondary parity error response enable controls the pex 8111?s response to addr ess and data parity errors on the pci bus secondary interface. 0 = pex 8111 must ignore parity errors detected and continue standard operation. a bridge must generate pari ty, regardless of whether parity error reporting is disabled. also, the pex 8111 must always forward posted write data with poisoning, from pci-to -pci express on a pci data parity error, regardless of this bit?s setting. 1 = pex 8111 must take its standard acti on when a parity error is detected. rw rw wo 0 1 secondary serr# enable controls forwarding of pci bus seconda ry interface serr# assertions to the primary interface (pci express). the pex 8111 transmits an err_fatal message on the primary inte rface when all of the following are true: serr# is asserted on the secondary interface this bit is set pci command register serr# enable bit is set or pci express device control register fatal error reporting enable or non-fatal error reporting enable bits are set rw rw wo 0 2 isa enable modifies the pex 8111?s response to isa i/o addresses that are enabled by the i/o base and i/o limit registers and located in the first 64 kb of the pci i/o address space. 1 = pex 8111 blocks forwarding from primary to secondary of i/o transactions addressing the last 768 bytes in each 1-kb block. in the opposite direction (secondary to primary), i/o transactions are forwarded when they address the last 768 bytes in each 1-kb block. rw rw wo 0 3 vga enable modifies the pex 8111?s response to vga-compatible addresses. when set, the bridge positively decodes and forwards the following accesses on the primary interface to the secondary interface (and, conversely, blocks the forwarding of these addresses from th e secondary to primary interface): memory accesses in the range 000a_0000h to 000b_ffffh i/o address in the first 64 kb of the i/o address space [address[31:16] for pci express are zero (0000h)] and where address[9:0] is in the range of 3b0h to 3bbh or 3c0h to 3dfh (inclusive of isa addr ess aliases ? address[15:10] can be any value and is not used in decoding) when the vga enable bit is set, vga address forwarding is independent of the isa enable bit value, and the i/o a ddress range and memory address ranges defined by the i/o base and i/o limit , memory base and memory limit , and prefetchable memory base and prefetchable memory limit registers. vga address forwarding is qualified by the pci command register i/o access enable and memory space enable bits. 0 = does not forward vga-compatib le memory and i/o addresses from the primary to secondary interface (a ddresses defined above), unless they are enabled for forwarding by the defined i/o and memory address ranges 1 = forwards vga-compatible memo ry and i/o addr esses (addresses defined above) from the primary interface to the secondary interface (when the i/o access enable and memory space enable bits are set), independent of the i/o and memory address ranges and isa enable bit rw rw wo 0
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 143 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 4 vga 16-bit decode enables the pex 8111 to provide 16-bit decoding of the vga i/o address, precluding the decoding of alias ad dresses every 1 kb. useful only when bit 3 ( vga enable ) of this register is also set to 1, enabling vga i/o decoding and bridge forwarding. enables system configurat ion software to select between 10- and 16-bit i/o address decoding for all vga i/o regist er accesses that are forwarded from primary to secondary, when the vga enable bit is set to 1. 0 = execute 10-bit address de codes on vga i/o accesses 1 = execute 16-bit address de codes on vga i/o accesses rw rw wo 0 5 master abort mode controls the pex 8111?s behavior when it receives a master abort termination on the pci bus or an unsupported request on pci express. 0 = do not report master aborts when pci express ur is received: ? return ffff_ffffh to pci bus for reads ? complete non-posted write normally on pci bus (assert trdy#) and discard the write data ? discard posted pci-to-pci express write data when pci transaction terminates with master abort: ? complete non-posted transa ction with unsupported request ? discard posted write data from pci express-to-pci 1 = report master aborts when pci express ur is received: ? complete reads and non-posted writes with pci target abort ? discard posted pci-to-pci express write data when pci transaction terminates with master abort: ? complete non-posted transa ction with unsupported request ? discard posted write data from pci express-to-pci ? transmit err_nonfatal message for posted writes rw rw wo 0 6 secondary bus reset 1 = forces pcirst# to be asserted on the secondary bus. additionally, the pex 8111 secondary bus inte rface, and buffers between the two interfaces (primary and secondary), must be initi alized to thei r default state. the primary bus interface and configur ation space registers must not be affected by setting this bit. because pcirst# is asserted while this bit is set, software must observe pr oper pci reset timing requirements. rw rw wo 0 7 fast back-to-back enable not supported . controls bridge ability to generate fast back-to-back transactions to various secondary interface devices. ro ro ? 0 register 15-31. (offset 3eh; bridgectl) bridge control (cont.) bit(s) description cfg mm ee default
forward bridge mode configuration registers plx technology, inc. 144 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8 primary discard timer in forward bridge mode, this bit do es not apply and is forced to 0. ro ro ? 0 9 secondary discard timer selects the number of pci clocks th at the pex 8111 waits for a master on the secondary interface to repeat a delayed transaction request. the counter starts after the completion (pci express completion associated with the delayed transaction request ) reaches the head of the pex 8111 downstream queue ( that is , all ordering requirements are satisfied and the pex 8111 is ready to complete th e delayed transaction with the originating master on the secondary bus). when the originating mast er does not repeat the transaction before the counter expires, the pex 8111 delete s the delayed tran saction from its queue and sets the discard timer status bit. 0 = secondary discard timer counts 2 15 pci clock periods 1 = secondary discard timer counts 2 10 pci clock periods rw rw wo 0 10 discard timer status set to 1 when the secondary discard timer expires and a delayed completion is discarded from a queue within the pex 8111. writing 1 clears this bit. rw1c rw1c wo 0 11 discard timer serr# enable when set to 1, enables the pex 8111 to generate an err_nonfatal message on the primary interface when the secondary discard timer expires and a delayed transaction is discarded from a queue within the pex 8111. 0 = does not generate err_nonfatal message on the primary interface as a result of the secondary discard timer expiration 1 = generates err_nonfatal messag e on the primary interface when the secondary discard timer expires and a delayed transaction is discarded from a queue within the pex 8111 rw rw wo 0 15:12 reserved rsvdp rsvdp ? 0h register 15-31. (offset 3eh; bridgectl) bridge control (cont.) bit(s) description cfg mm ee default
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 145 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.7 pci-compatible extended capability registers for pci express interface register 15-32. (offset 40h; pwrmngid) power management capability id bit(s) description cfg mm ee default 7:0 power management capability id specifies the power mana gement capability id. ro ro ? 01h register 15-33. (offset 41h; pwrmngnext) power management next capability pointer bit(s) description cfg mm ee default 7:0 pci power management ne xt capability pointer points to the first location of the next item in the new capabilities linked list, message signaled interrupts. ro rw wo 50h register 15-34. (offset 42h; pwrmng cap) power management capabilities bit(s) description cfg mm ee default 2:0 pme version default 010b indicates compliance with the pci power mgmt. r1.1. ro rw wo 010b 3 pme clock does not apply to pci express; therefore, must always be a value of 0. ro ro ? 0 4 reserved rsvdp rsvdp ? 0 5 device-specific initialization indicates that the pex 8111 requires special initialization following a transition to the d0_uni nitialized state befo re the generic class device driver uses it. ro rw wo 0 8:6 aux current reports the 3.3vaux auxiliary cu rrent requirements for the pci function. when pci backplane pm eout# generation from d3cold is not supported by the function, must return a value of 000b. ro rw wo 000b 9 d1 support indicates whether the pex 8111 supports the d1 state. ro rw wo 1 10 d2 support indicates whether the pex 8111 supports the d2 state. by default, d2 is not supported ; however, with additional circuitry, the pex 8111 can support d2. ro rw wo 0 15:11 pme support default 11001b indicates that th e corresponding pex 8111 port forwards pme messages in the d0, d3hot, and d3cold power states. xxxx1b = assertable from d0 xxx1xb = assertable from d1 xx1xxb = assertable from d2 x1xxxb = assertable from d3hot 1xxxxb = assertable from d3cold ro rw wo 11001b
forward bridge mode configuration registers plx technology, inc. 146 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-35. (offset 44h; pwrmngcs r) power management control/status bit(s) description cfg mm ee default 1:0 power state used to determine or chan ge the current power state. 00b = d0 01b = d1 10b = d2 11b = d3hot a transition from state d3 to state d0 causes a hot reset to occur. in states d1 and d2, when the corresponding d1 support and d2 support bits are set, pci memory and i/o accesses are disabl ed, as well as the pci interrupt, and only configuration cycles are allowed. in state d3hot, these func tions are also disabled. rw rw wo 00b 7:2 reserved rsvdp rsvdp ? 0h 8 pme enable enables a pme message to transmit upstream. rw rw wo 0 12:9 data select not supported. always returns a value of 0h. ro ro ? 0h 14:13 data scale not supported. always returns a value of 00b. ro ro ? 00b 15 pme status indicates that a pme message was transmitted upstream. writing 1 clears this bit. rw1c rw1c ? 0 register 15-36. (offset 46h; pwrmngbridge) power management bridge support bit(s) description cfg mm ee default 5:0 reserved rsvdp rsvdp ? 0h 6 b2/b3 support not supported in forward bridge mode; therefore, forced to 0. ro ro ? 0 7 bus power/clock control enable not supported in forward bridge mode; therefore, forced to 0. ro ro ? 0 register 15-37. (offset 47h; pw rmngdata) power management data bit(s) description cfg mm ee default 7:0 power management data not supported. always returns a value of 0h. ro ro ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 147 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-38. (offset 48h; d evspecctl) device-specific control bit(s) description cfg mm ee default 0 blind prefetch enable 0 = memory read command on the pci bus that targets the pci express memory space causes only 1 word to be read from the pci express interface. 1 = memory read command on the pci bus that targets the pci express memory space causes at least one cache line to be read from the pci express interface. additional dwor ds can be read by setting the pci control register programmed prefetch size field. rw rw wo 0 1 pci base address 0 enable 1 = enables the pci base address 0 space for memory-mapped access to the configuration registers and shared memory. pci base address 0 is also enabled when the bar0enb# ball is low. rw rw wo 0 2 l2 enable does not apply to fo rward bridge mode. rw rw wo 0 3 pmu power off 1 = link transitioned to the l2/l3 read y state, and is ready to power down ro ro ? 0 7:4 pmu link state indicates the link state. 0001b = l0 0010b = l0s 0100b = l1 1000b = l2 all other values are reserved . ro ro ? ? 9:8 crs retry control does not apply to fo rward bridge mode. rw rw wo 00b 10 wake out enable 1 = wakeout# signal is asserted when pmein# is asserted and the link remains in the l2 state rw rw wo 0 11 beacon generate enable 1 = beacon is generated when pmein# is asserted and the link remains in the l2 state rw rw wo 0 12 beacon detect enable does not apply to fo rward bridge mode. rw rw wo 0 13 pll locked high when internal pll is locked. ro ro ? ? 15:14 reserved rsvdp rsvdp ? 00b 20:16 link training and st atus state machine factory test only. ro ro ? ? 31:21 reserved rsvdp rsvdp ? 0h
forward bridge mode configuration registers plx technology, inc. 148 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-39. (offset 50h; msiid) message signaled interrupts capability id bit(s) description cfg mm ee default 7:0 msi capability id specifies the message signale d interrupts capability id. ro ro ? 5h register 15-40. (offset 51h; msinext) message signaled interrupts next capability pointer bit(s) description cfg mm ee default 7:0 msi next capability pointer points to the first location of the next item in the new capabilities linked list, pci express capability. ro rw wo 60h register 15-41. (offset 52h; msictl) message signaled interrupts control bit(s) description cfg mm ee default 0 msi enable when set: enables the pex 8111 to use msi to request service virtual interrupt support for intern al interrupt sources are disabled rw rw wo 0 3:1 multiple message capable system software reads this field to determine the num ber of requested messages. the number of requested messages must be aligned to a power of two (when a function requires th ree messages, it requests four). value number of messages requested 000b 1 001b 2 010b 4 011b 8 100b 16 101b 32 110b, 111b reserved ro ro ? 000b 6:4 multiple message enable system software writes to this fiel d to indicate the number of allocated messages (equal to or less than the number of requested messages). the number of allocated messages is aligned to a power of two. value number of messages requested 000b 1 001b 2 010b 4 011b 8 100b 16 101b 32 110b, 111b reserved rw rw wo 000b 7 msi 64-bit address capable 1 = pex 8111 is capable of gene rating a 64-bit message address ro rw wo 1 8 per vector masking capable not supported. forced to 0. ro ro ? 0 15:9 reserved rsvdp rsvdp ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 149 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-42. (offset 54h; msiaddr) message signaled interrupts address bit(s) description cfg mm ee default 1:0 reserved rsvdp rsvdp ? 00b 31:2 msi address when the message signaled interrupts control register msi enable bit is set, the register contents specify the dword-aligned address for the msi memory write transaction. address bits [1:0] are driven to zero (00b) during the address phase. rw rw wo 0h register 15-43. (offset 58h; msiupperaddr) message signaled inte rrupts upper address bit(s) description cfg mm ee default 31:0 msi upper address optionally implemented only when th e pex 8111 supports a 64-bit message address when the message signaled in terrupts control register msi 64-bit address capable bit is set. when the message signaled interrupts control register msi enable bit is set, the register contents specify the upper 32 bits of a 64-bit message. when the register contents are zero (0h), the pex 8111 uses the 32-bit address specified by the message signaled interrupts address register. rw rw wo 0h register 15-44. (offset 5ch; msidata) message signaled interrupts data bit(s) description cfg mm ee default 15:0 msi data when the message signaled interrupts control register msi enable bit is set, the message data is driven onto the lower word of the ad bus (ad[15:0]) of the memory write transaction da ta phase. the upper word (ad[31:16]) is always cleared to 0h. rw rw wo 0h 31:16 reserved rsvdp rsvdp ? 0h
forward bridge mode configuration registers plx technology, inc. 150 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-45. (offset 60h; pciexid) pci express capability id bit(s) description cfg mm ee default 7:0 pci express capability id specifies the pci express capability id. ro rw ? 10h register 15-46. (offset 61h; pciexnext) pci express next capability pointer bit(s) description cfg mm ee default 7:0 pci express next capability pointer points to the first location of the next item in the new capabilities linked list. ro rw wo 0h register 15-47. (offset 62h; pciexcap) pci express capabilities bit(s) description cfg mm ee default 3:0 capability version indicates the pci express capabi lity structure version number. ro rw wo 1h 7:4 device/port type indicates the type of pc i express logical device. 0000b = pci express endpoint device 0001b = legacy pci express endpoint device 0100b = root port of pci express root complex 0101b = upstream port of pci express switch 0110b = downstream port of pci express switch 0111b = pci express-to-pci/pci-x bridge 1000b = pci/pci-x-to-pci express bridge all other values are reserved . ro rw wo 0111b 8 slot implemented 1 = indicates that the pci express link associated with this port is connected to a slot ro rw wo 0 13:9 interrupt message number when this function is allocated more than one msi interrupt number, this field must contai n the offset between the base message data and the msi message generated when slot status register status bi ts of this capability structure are set. for the field to be correct, hardware must update it when the number of msi messages assigned to the pex 8111 changes. ro ro ? 0h 15:14 reserved rsvdp rsvdp ? 00b
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 151 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-48. (offset 64h; devcap) device capabilities bit(s) description cfg mm ee default 2:0 maximum payload size supported indicates the maximum pa yload size that the pe x 8111 supports for tlps. 000b = 128 bytes all other values are reserved . note: because the pex 8111 supports a maximum payload size of only 128 bytes, this field is hardwired to 000b. ro ro ? 000b 4:3 phantom functions supported not supported. hardwired to 00b. indicates support for the use of unc laimed function numbers to extend the number of outstanding transactions allowed, by logically combining unclaimed function numbers (called phantom functions) with the tag identifier. ro ro ? 00b 5 extended tag field supported indicates the maximum supporte d size of the tag field. 0 = 5-bit tag field is supported 1 = 8-bit tag field is supported note: 8-bit tag field support must be enabled by the corresponding control field in the pci express device control register. ro rw wo 0 8:6 endpoint l0s acceptable latency indicates the acceptable to tal latency that an endpoint withstands due to the transition from the l0s state to the l0 state. it is essentially an indirect measure of the endpoint internal buffering. power management software uses th e reported l0s acceptable latency number to compare against the l0s exit latencies reported by all components comprising the data path from this endpoi nt to the root complex root port, to determine whether active state link pm l0s entry is used with no performance loss. 000b = less than 64 ns 001b = 64 ns to less than 128 ns 010b = 128 ns to less than 256 ns 011b = 256 ns to less than 512 ns 100b = 512 ns to 1 s 101b = 1 s to less than 2 s 110b = 2 to 4 s 111b = more than 4 s ro rw wo 000b
forward bridge mode configuration registers plx technology, inc. 152 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 11:9 endpoint l1 acceptable latency indicates the acceptable to tal latency that an endpoint withstands due to the transition from the l1 state to the l0 state. it is essentially an indirect measure of the endpoint internal buffering. power management software uses the report l1 ac ceptable latency number to compare against the l1 exit la tencies reported by all components comprising the data path from this endpoi nt to the root complex root port, to determine whether active state link pm l1 entry is used with no performance loss. 000b = less than 1 s 001b = 1 s to less than 2 s 010b = 2 s to less than 4 s 011b = 4 s to less than 8 s 100b = 8 s to less than 16 s 101b = 16 s to less than 32 s 110b = 32 to 64 s 111b = more than 64 s ro rw wo 000b 12 attention button present not supported. forced to 0. ro ro ? 0 13 attention indica tor present. not supported. forced to 0. ro ro ? 0 14 power indicator present not supported. forced to 0. ro ro ? 0 17:15 reserved rsvdp rsvdp ? 000b 25:18 captured slot power limit value specifies the upper limit on power supp lied by slot in combination with the slot power limit scale value. power limit (in watts) is calculated by multiplying the value in this field by the value in the slot power limit scale field. value is set by the set slot power limit message. ro rw wo 0h 27:26 captured slot power limit scale specifies the scale used for the slot power limit value. value is set by the set slot power limit message. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x ro rw wo 00b 31:28 reserved rsvdp rsvdp ? 0h register 15-48. (offset 64h; devcap) device capabilities (cont.) bit(s) description cfg mm ee default
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 153 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-49. (offset 68h; devctl) pci express device control bit(s) description cfg mm ee default 0 correctable error reporting enable controls correctable error reporting. when a correctable error is detected in forward bridge mode and this bit is set, an err_cor message is transmitted to the root complex. rw rw wo 0 1 non-fatal error reporting enable controls non-fatal error reporting. when a non-fatal error is detected in fo rward bridge mode an d this bit is set, an err_nonfatal message is transmitted to the root complex. rw rw wo 0 2 fatal error reporting enable controls fatal error reporting. when a fatal error is detected in forw ard bridge mode and this bit is set, an err_fatal message is transmitted to the root complex. rw rw wo 0 3 unsupported request reporting enable controls unsupported request reporting. when an unsupported request response is received from the pci express in forward bridge mode and this bit is set, a err_nonfatal message is transmitted to the root complex. rw rw wo 0 4 enable relaxed ordering not supported . forced to 0. 1 = pex 8111 is permitted to set the relaxe d ordering bit in the attributes field of transactions it initiates that do not require strong write ordering ro ro ? 0 7:5 maximum payload size sets the maximum tlp payload size for the pex 8111. as a receiver, the pex 8111 must handle tlps as large as the set value; as transmitter, the pex 8111 must not generate tlps exceeding the set va lue. permissible values for transmitted tlps are indicated in the device capabilities register maximum payload size supported field. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = reserved rw rw wo 000b
forward bridge mode configuration registers plx technology, inc. 154 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8 extended tag field enable 0 = pex 8111 is restricted to a 5-bit tag field 1 = enables pex 8111 to use an 8-bit tag field as a requester forced to 0 when the device capabilities register extended tag field supported bit is cleared. rw rw wo 0 9 phantom function enable not supported. hardwired to 0. ro ro ? 0 10 auxiliary (aux) power pm enable not supported. hardwired to 0. 1 = enables a device to draw aux power independent of pme aux power devices that require aux power on lega cy operating systems must continue to indicate pme aux powe r requirements. aux po wer is allocated as requested in the power management capabilities register aux current field, independent of the power management control/status register pme enable bit. ro ro ? 0 11 enable no snoop not supported. hardwired to 0. 1 = pex 8111 is permitted to set the no snoop bit in the requester attributes of transactions it initiates that do not require hardware-enforced cache coherency setting this bit to 1 does not ca use a device to blindly set the no snoop attribute on all transactions that it initiates. although th is bit is set to 1, a device only sets the no snoop attribute on a transaction when it can guarantee that the transaction address is not stored in a system cache. the pex 8111 never sets the no snoop attribute; therefore, this bit is forced to 0. ro ro ? 0 14:12 maximum read request size the value specified in this register is the upper boundary of the pci control register programmed prefetch size field if the device-specific control register blind prefetch enable bit is set. sets the maximum read request size for the device as a requester. the pex 8111 must not genera te read requests with a size that exceeds the set value. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = reserved rw rw wo 010b 15 bridge configuration retry enable 0 = pex 8111 does not gene rate completions with completion retry status on behalf of pci express-to-pci configuration transactions. 1 = pex 8111 generates comp letions with completion retry status on behalf of pci express-to-pci configuration transactions. occurs after a delay determined by the crs timer register. rw rw wo 0 register 15-49. (offset 68h; devctl) pci express device control (cont.) bit(s) description cfg mm ee default
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 155 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-50. (offset 6ah; devstat) pci express device status bit(s) description cfg mm ee default 0 correctable error detected indicates correctable errors detected status. errors are logged in this register, regardless of whether error reporting is enabled in the pci express device control register. rw1c rw1c ? 0 1 non-fatal error detected indicates non-fatal errors detected status. e rrors are logged in this register, regardless of whether error reporting is enabled in the pci express device control register. rw1c rw1c ? 0 2 fatal error detected indicates fatal erro rs detected status. errors are logged in this register, regardless of whether error reporting is enabled in the pci express device control register. rw1c rw1c ? 0 3 unsupported request detected indicates that the pex 8111 received an unsupported request. errors are logged in this register, regardless of whether error reporting is enabled in the pci express device control register. rw1c rw1c ? 0 4 aux power detected devices that require aux power repor t this bit as set when the pex 8111 detects aux power. ro ro ? 0 5 transactions pending because the pex 8111 does not internally generate non-posted transactions, this bit is forced to 0. ro ro ? 0 15:6 reserved rsvdz rsvdz ? 0h
forward bridge mode configuration registers plx technology, inc. 156 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-51. (offset 6ch; linkcap) link capabilities bit(s) description cfg mm ee default 3:0 maximum link speed indicates the maximum link speed of the given pci express link. set to 0001b for 2.5 gbps. all other values are reserved . ro ro ? 0001b 9:4 maximum link width indicates the maximum width of the give n pci express link. by default, the pex 8111 has an x1 link; therefore, th is field is hardwired to 00_0001b. all other values are not supported . ro ro ? 00_0001b 11:10 active state link pm support indicates the level of active state po wer management suppor ted on the given pci express link. 01b = l0s entry supported 11b = l0s and l1 supported 00b, 10b = reserved ro rw wo 11b 14:12 l0s exit latency indicates the l0s exit latency for th e given pci express link. the value reported indicates the length of time th is port requires to complete transition from l0s to l0. 000b = less than 64 ns 001b = 64 ns to less than 128 ns 010b = 128 ns to less than 256 ns 011b = 256 ns to less than 512 ns 100b = 512 ns to 1 s 101b = 1 s to less than 2 s 110b = 2 to 4 s 111b = more than 4 s ro rw wo 100b 17:15 l1 exit latency indicates the l1 exit latency for th e given pci express link. the value reported indicates the length of time th is port requires to complete transition from l1 to l0. 000b = less than 1 s 001b = 1 s to less than 2 s 010b = 2 s to less than 4 s 011b = 4 s to less than 8 s 100b = 8 s to less than 16 s 101b = 16 s to less than 32 s 110b = 32 to 64 s 111b = more than 64 s ro rw wo 100b 23:18 reserved rsvdp rsvdp ? 0h 31:24 port number indicates the pci express port number for the given pci express link. ro rw wo 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 157 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-52. (offset 70h; linkctl) link control bit(s) description cfg mm ee default 1:0 active state link pm control controls the level of active state pm supported on the given pci express link. 00b = disabled 01b = l0s entry supported 10b = reserved 11b = l0s and l1 entry supported note: ?l0s entry enabled? indi cates the transmitter entering l0s. rw rw wo 00b 2 reserved rsvdp rsvdp ? 0 3 read completion boundary (rcb) control 0 = read completion boundary is 64 bytes 1 = read completion boundary is 128 bytes rw rw wo 0 4 link disable does not apply to forward bridge mode. ro ro ? 0 5 retrain link does not apply to forward bridge mode. ro ro ? 0 6 common clock configuration 0 = indicates that the pex 811 1 and the component at the opposite end of the link are operating with asynchronous reference clock. components utilize this common clock configuration information to report the correct l0s and l1 exit latencies. 1 = indicates that the pex 811 1 and the component at the opposite end of the link are operating with a distributed common reference clock. rw rw wo 0 7 extended sync 1 = forces extended transmission of fts ordered sets in fts and extra ts2 at exit from l1 prior to entering l0. this mode provides external devices moni toring the link time to achieve bit and symbol lock before th e link enters the l0 state and resumes communication. rw rw wo 0 15:8 reserved rsvdp rsvdp ? 0h
forward bridge mode configuration registers plx technology, inc. 158 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-53. (offset 72h; linkstat) link status bit(s) description cfg mm ee default 3:0 link speed indicates the negotiated link speed of the given pci express link. set to 0001b for 2.5 gbps. all other values are reserved . ro ro ? 0001b 9:4 negotiated link width indicates the negotia ted width of the given pci e xpress link. by default, the pex 8111 has an x1 link; therefore, this field is hardwired to 00_0001b. all other values are not supported . ro ro ? 00_0001b 10 link training error does not apply to forward bridge mode. ro ro ? 0 11 link training does not apply to forward bridge mode. ro ro ? 0 12 slot clock configuration indicates that the pex 8111 uses the sa me physical refe rence clock that the platform provides on the connector. when the pex 8111 uses an independent clock irresp ective of the presence of a reference on the connector, this bit must be cleared. hwinit rw wo 0 15:13 reserved rsvdz rsvdz ? 000b
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 159 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-54. (offset 74h; slotcap) slot capabilities bit(s) description cfg mm ee default 0 attention button present not supported . forced to 0. ro ro ? 0 1 power controller present not supported . forced to 0. ro ro ? 0 2 mrl sensor present not supported . forced to 0. ro ro ? 0 3 attention indicator present not supported . forced to 0. ro ro ? 0 4 power indicator present not supported . forced to 0. ro ro ? 0 5 hot plug surprise not supported . forced to 0. ro ro ? 0 6 hot plug capable not supported . the pex 8111 does not support hot plug operations; therefore, this bit is forced to 0. ro ro ? 0 14:7 slot power limit value does not apply to fo rward bridge mode. ro rw wo 25d 16:15 slot power limit scale does not apply to fo rward bridge mode. ro rw wo 00b 18:17 reserved rsvdp rsvdp ? 00b 31:19 physical slot number not supported. forced to 0h. ro ro ? 0h
forward bridge mode configuration registers plx technology, inc. 160 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-55. (offset 78h; slotctl) slot control bit(s) description cfg mm ee default 0 attention button pressed enable not supported . forced to 0. rw rw wo 0 1 power fault detected enable not supported . forced to 0. rw rw wo 0 2 mrl sensor changed enable not supported . forced to 0. rw rw wo 0 3 presence detect changed enable not supported . forced to 0. rw rw wo 0 4 command completed interrupt enable not supported . forced to 0. rw rw wo 0 5 hot plug interrupt enable not supported . forced to 0. rw rw wo 0 7:6 attention indicator control not supported . forced to 0. rw rw wo 00b 9:8 power indicator control not supported . forced to 00b. rw rw wo 00b 10 power controller control not supported . forced to 0. rw rw wo 0 15:11 reserved rsvdp rsvdp ? 0h register 15-56. (offset 7a h; slotstat) slot status bit(s) description cfg mm ee default 0 attention button pressed not supported . forced to 0. ro ro ? 0 1 power fault detected not supported . forced to 0. ro ro ? 0 2 mrl sensor changed not supported . forced to 0. ro ro ? 0 3 presence detect changed not supported . forced to 0. ro ro ? 0 4 command completed not supported . forced to 0. ro ro ? 0 5 mrl sensor state not supported . forced to 0. ro ro ? 0 6 presence detect state not supported . forced to 1. ro ro ? 1 15:7 reserved rsvdp rsvdp ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 161 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-57. (offset 84h; mainindex) main control register index bit(s) description cfg mm ee default 11:0 main control register index selects a main control register that is accessed by way of the main control register data register. rw rw wo 0h 31:12 reserved rsvdp rsvdp ? 0h register 15-58. (offset 88h; maindata) main control register data bit(s) description cfg mm ee default 31:0 main control register data writes to and reads from this register are mapped to a main control register selected by the main control register index register. rw rw wo 0h
forward bridge mode configuration registers plx technology, inc. 162 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.8 pci express extended capability registers 15.8.1 pci express power budgeting registers register 15-59. (offset 100h; pwrcaphdr) power budgeting capability header bit(s) description cfg mm ee default 15:0 pci express extended capability id pci-sig-defined id number that indi cates the nature and format of the extended capability. ro rw wo 4h 19:16 capability version pci-sig-defined version number that indicates the version of the capability structure present. ro rw wo 1h 31:20 next capability offset contains the offset to the next pci e xpress capability structure, or 000h when no other items exist in the new capabilities linked list. set to 110h when serial number capability must be enabled. ro rw wo 000h register 15-60. (offset 104h; pwrdatasel) power budgeting data select bit(s) description cfg mm ee default 7:0 data select register indexes the power budgeting data reported through the power budgeting data register. selects the dword of powe r budgeting data that is to appear in the power budgeting data register. the pex 8111 supports values from 0 to 31 for this field. for values greater than 31, a value of 0h is returned when the power budgeting data register is read. rw rw wo 0h 31:8 reserved rsvdp rsvdp ? 0h
june, 2006 pci express power budgeting registers pex 8111bb expresslane pci express-to-pci bridge data book 163 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-61 returns the dword of power budgeting data selected by the power budgeting data select register. when the power budgeting data select register contains a valu e greater than or equal to the number of operating conditions for which the pe x 8111 provides power information, this register returns all zeros (0). the pex 8111 supports 32 operating conditions. register 15-61. (offset 108h; pwrdata) power budgeting data bit(s) description cfg mm ee default 7:0 base power specifies (in watts) the base power value in the given operating condition. this value must be multiplied by the data scale , to produce the actual power consumption value. ro rw wo 0h 9:8 data scale specifies the scale to apply to the base power value. the pex 8111 power consumption is determin ed by multiplying the base power field contents with the value corresponding to the encoding returned by this field. 00b = 1.0x 10b = 0.01x 01b = 0.1x 11b = 0.001x ro rw wo 00b 12:10 pm sub-state specifies the power management sub- state of the operating condition being described. 000b = default sub-state all other values = devi ce-specific sub-state ro rw wo 000b 14:13 pm state specifies the power management st ate of the operating condition being described. a device returns 11b in this field and aux or pme aux in the pm type field to specify the d3cold pm state. an encoding of 11b along with any other pm type field value specifies the d3hot state. 00b = d0 10b = d2 01b = d1 11b = d3 ro rw wo 00b 17:15 pm type specifies the type of opera ting condition be ing described. 000b = pme aux 011b = sustained 001b = auxiliary 111b = maximum 010b = idle all other values = reserved ro rw wo 000b 20:18 power rail specifies the power rail of the operating condition being described. 000b = power (12v) 111b = thermal 001b = power (3.3v) all other values = reserved 010b = power (1.8v) ro rw wo 000b 31:21 reserved rsvdp rsvdp ? 0h register 15-62. (offset 10ch; pw rbudcap) power budget capability bit(s) description cfg mm ee default 0 system allocated 1 = indicates that the pex 8111 power b udget is included within the system power budget, and software is to ig nore reported power budgeting data for power budgeting decisions ro rw wo 0 31:1 reserved rsvdp rsvdp ? 0h
forward bridge mode configuration registers plx technology, inc. 164 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.8.2 pci express serial number registers register 15-63. (offset 110h; sercaphdr) serial number capability header bit(s) description cfg mm ee default 15:0 pci express extended capability id pci-sig-defined id number that indi cates the nature and format of the extended capability. forced to 0 when serial number capability is disabled. ro ro ? 3h 19:16 capability version pci-sig-defined version number that indicates the version of the capability structure present. forced to 0h when se rial number capability is disabled. ro ro ? 1h 31:20 next capability offset contains the offset to the next pci e xpress capability st ructure or 000h when no other items exist in the ne w capabilities linked list. ro ro ? 000h register 15-64. (offset 114h; sernumlow) serial number low (lower dword) bit(s) description cfg mm ee default 31:0 pci express device serial number contains the lower dword of the ieee-defined 64-bit extended unique identifier. includes a 24-bit company id value assigned by the ieee registration authority a nd a 40-bit extension identifier assigned by the manufacturer. forced to 0h when se rial number capability is disabled. ro rw wo 0h register 15-65. (offset 118h; sernumhi) serial number hi (upper dword) bit(s) description cfg mm ee default 31:0 pci express device serial number contains the upper dword of the ie ee defined 64-bi t extended unique identifier. includes a 24-bit company id value assigned by the ieee registration authority a nd a 40-bit extension identifier assigned by the manufacturer. forced to 0h when se rial number capability is disabled. ro rw wo 0h
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 165 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15.9 main control registers register 15-66. (offset 1000h; devinit) device initialization bit(s) description cfg mm 3:0 pclko clock frequency controls the pclko ball frequency. when cleared to 0000b, the clock is stopped and remains at a logic low (0v) dc value. non-zero values represent divisors of the 100-mhz refclk. the default value is 0011b, representing a frequency of 66 mhz. 0000b = 0 0001b = 100 0010b = 50 0011b = 33.3/66 (when m66en is hi gh, pclko frequency is 66 mhz) 0100b = 25 0101b = 20 0110b = 16.7 0111b = 14.3 1000b = 12.5 1001b = 11.1 1010b = 10 1011b = 9.1 1100b = 8.3 1101b = 7.7 1110b = 7.1 1111b = 6.7 rw 0011b 4 pci express enable 0 = all configuration accesses to the pex 8111, configured in forward bridge mode, result in a completion status of config uration request retry status. 1 = pex 8111 responds normally to pci expres s configuration access es. automatically set when a valid serial eeprom is not detected. rw 0 5 pci enable 0 = all pci accesses to the pex 8111 re sult in a target retry response 1 = pex 8111 responds normally to pci accesses automatically set when a valid serial eeprom is not detected. rw 0 31:6 reserved rsvdp 0h
forward bridge mode configuration registers plx technology, inc. 166 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-67. (offset 1004h; eectl) serial eeprom control bit(s) description cfg mm 7:0 serial eeprom write data determines the byte written to the serial eeprom when the serial eeprom by te write start bit is set. represents an op code, address, or data being written to the serial eeprom. rw 0h 15:8 serial eeprom read data determines the byte read from the serial eeprom when the serial eeprom by te read start bit is set. ro ? 16 serial eeprom byte write start 1 = value in the serial eeprom write data field is written to the serial eeprom automatically cleared when the write operation is complete. rw 0 17 serial eeprom byte read start 1 = a byte is read from the serial eeprom, and accessed using the serial eeprom read data field automatically cleared when the read operation is complete. rw 0 18 serial eeprom chip select enable 1 = serial eeprom chip select is enabled rw 0 19 serial eeprom busy 1 = serial eeprom controll er is busy performing a byte read or write operation an interrupt is generated when this bit goes false. ro 0 20 serial eeprom valid 1 = serial eeprom with 5ah in the first byte is detected ro ? 21 serial eeprom present set when the serial eeprom cont roller determines that a serial eeprom is connected to the pex 8111. ro ? 22 serial eeprom chip select active set when the eecs# ball to the serial eeprom is active. the chip select can be active across multiple byte operations. ro ? 24:23 serial eeprom address width reports the installed serial ee prom?s addressing width. when the addressing width cannot be determined, 00b is returned. a non-zero value is reported only when the validation signature ( 5ah ) is successfully read from the first serial eeprom location. 00b = undetermined 01b = 1 byte 10b = 2 bytes 11b = 3 bytes ro ? 30:25 reserved rsvdp 0h 31 serial eeprom reload writing 1 to this bit causes the serial eeprom controller to perform an initialization sequence. configuration registers and shared memo ry are loaded from the serial eeprom. reading this bit returns 0 while initialization is in progress, and 1 when initialization is complete. rw 0
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 167 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-68. (offset 1008h; eeclk freq) serial eeprom clock frequency bit(s) description access default 2:0 serial eeprom clock frequency controls the eeclk ball frequency. 000b = 2 mhz 001b = 5 mhz 010b = 8.3 mhz 011b = 10 mhz 100b = 12.5 mhz 101b = 16.7 mhz 110b = 25 mhz 111b = reserved rw 000b 31:3 reserved rsvdp 0h register 15-69. (offset 100ch; pcictl) pci control bit(s) description access default 0 pci multi-level arbiter 0 = all pci requesters are placed into a singl e-level round-robin arbiter, each with equal access to the pci bus 1 = two-level arbiter is selected rw 0 3:1 pci arbiter park select determines which pci master controller is granted the pci bus when there are no pending requests. 000b = last grantee 001b = pci express interface 010b, 011b = reserved 100b = external requester 0 101b = external requester 1 110b = external requester 2 111b = external requester 3 rw 000b 4 bridge mode reflects the forward ball status. when low, the pex 8111 operates as a reverse bridge (pci-to-pci express). when high, the pex 8111 operates as a fo rward bridge (pci express-to-pci). ro ? 5 pci external arbiter reflects the extarb ball state. when low, the pex 8111 enables its internal ar biter. it then expect s external requests on req[3:0]# and issues bu s grants on gnt[3:0]#. when high, the pex 8111 asserts req0# and expects gnt0# from an external arbiter. ro ? 6 locked transaction enable 0 = pci express memory read lock requests are completed with ur status, and the pci lock# ball is not driven rw 0 7 m66en reflects the m66en ball state. when low, the pex 8111 pci bus is operating at 33 mhz. when high, the pex 8111 pci bus is operating at 66 mhz. ro 0
forward bridge mode configuration registers plx technology, inc. 168 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 15:8 pci-to-pci express retry count does not apply to forward bridge mode. rw 80h 23:16 pci express-to-pci retry count determines the number of times to retry a pci express-to-pci transaction before aborting the transfer (in units of 2 4 retries). 0h = indicates that the tran saction is retried forever 255 = selects a retry count of 2 24 rw 0h 24 memory read line enable 0 = pex 8111 issues a memory read command for transactions that do not start on a cache boundary. 1 = memory read line command is issued when a transaction is not aligned to a cache boundary in prefetchable address space, and the bu rst transfer size is at least one cache line of data. the pci burst is stopped at the cach e line boundary when the burst transfer size is less than one cache line of data or when a memory read multiple command is started. rw 1 25 memory read multiple enable 0 = pex 8111 issues a memory read command for transactions that start on a cache boundary. 1 = memory read multiple command is issued when a transaction is aligned to a cache boundary in prefetchable address space, and the bu rst transfer size is at least one cache line of data. the pci burst continues when the burst transfer size remains greater than or equal to one cache line of data. rw 1 26 early byte enables expected 0 = pex 8111 expects pci bytes enables to be valid after irdy# is asserted 1 = pex 8111 expects the pci byte enables to be valid in the cloc k tick following the address phase for maximum compatibility with non-compli ant pci devices, clear this bit to 0. for maximum performance, set this bit to 1. rw 0 29:27 programmed prefetch size valid only for memory read line and memory read multiple transactions, or memory read transactions accessing prefetchable memory space with the device-specific control register blind prefetch enable bit set. determines the number of bytes requested from the pci express interface as a result of a pci-to-pci express read. if a prefetch size is specified, the cache li ne boundary requirements of the memory read line and memory read multiple commands are di sabled and the number of bytes requested will match the prefetch size. enable feature only when the pci initiator re ads all requested data without disconnecting. otherwise, performance is impacted. the prefetch size is limited by the pci express device control register maximum read request size field. 000b = disabled 001b = 64 bytes 010b = 128 bytes 011b = 256 bytes 100b = 512 bytes 101b = 1,024 bytes 110b = 2,048 bytes 111b = 4,096 bytes (4 kb; refer to note) note: if the programmed prefetch size is 4 kb, the tlp controller configuration 0 register limit completion flow control credit bit must be set. rw 000b 31:30 reserved rsvdp 00b register 15-69. (offset 100ch; pcictl) pci control (cont.) bit(s) description access default
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 169 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-70. (offset 1010h; pcieirqenb) pci express interrupt request enable bit(s) description access default 0 serial eeprom done interrupt enable 1 = enables a pci express interrupt to generate when a serial eeprom read or write transaction completes note: refer to section 5.1, ?forward bridge pci interrupts,? for further details. rw 0 1 gpio interrupt enable 1 = enables a pci express interrupt to generate when an interr upt is active from one of the gpio balls rw 0 2 reserved rsvdp 0 3 pci express-to-pci retry interrupt enable 1 = enables a pci express interrupt to genera te when the pci express-to-pci retry count is reached rw 0 4 mailbox 0 interrupt enable 1 = enables a pci express interrupt to generate when mailbox 0 is written rw 0 5 mailbox 1 interrupt enable 1 = enables a pci express interrupt to generate when mailbox 1 is written rw 0 6 mailbox 2 interrupt enable 1 = enables a pci express interrupt to generate when mailbox 2 is written rw 0 7 mailbox 3 interrupt enable 1 = enables a pci express interrupt to generate when mailbox 3 is written rw 0 8 unsupported request interrupt enable 1 = enables a pci interrupt to be generated when an unsupporte d request completion response is received from the pci express interface rw 0 30:9 reserved rsvdp 0h 31 pci express internal interrupt enable 1 = enables a pci express interrupt to be ge nerated as a result of an internal pex 8111 interrupt source. the internal interrupt is se rviced as a message signaled interrupt (msi) or virtual wire interrupt. note: refer to section 5.1, ?forward bridge pci interrupts,? for further details. rw 1
forward bridge mode configuration registers plx technology, inc. 170 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-71. (offset 1018h; irqstat) interrupt request status bit(s) description access default 0 serial eeprom done interrupt set when a serial eeprom read or write transaction completes. writing 1 clears this status bit. rw1c 0 1 gpio interrupt conveys the interrupt status for the four gpio balls. set i ndependently of the gpio interrupt enable bits. this bit is an or of the four individual gp io status bits. 1 = general-purpose i/o status register is read to determine the cause of the interrupt ro 0 2 reserved rsvdp 0 3 pci express-to-pci retry interrupt set when the pci express-to-pci retry count is reached. writing 1 clea rs this status bit. rw1c 0 4 mailbox 0 interrupt set when mailbox 0 is writte n. writing 1 clears this bit. rw1c 0 5 mailbox 1 interrupt set when mailbox 1 is writte n. writing 1 clears this bit. rw1c 0 6 mailbox 2 interrupt set when mailbox 2 is writte n. writing 1 clears this bit. rw1c 0 7 mailbox 3 interrupt set when mailbox 3 is writte n. writing 1 clears this bit. rw1c 0 8 unsupported request interrupt set when an unsupported request completion is received from the pci express interface, provided that the pci express interr upt request enable register unsupported request interrupt enable bit is set. rw1c 0 31:9 reserved rsvdz 0h
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 171 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-72. (offset 101ch; power) power bit(s) description access default 7:0 power compare 0 specifies the power required for th is device and downstream pci de vices. it is compared with the device capabilities register captured slot power limit value field. when the captured slot power limit value is greater than or equal to this field, the pwr_ok signal is asserted. used when the device capabilities register captured slot power limit scale field is 00b (scale = 1.0x). rw 0h 15:8 power compare 1 specifies the power required for th is device and downstream pci de vices. it is compared with the device capabilities register captured slot power limit value field. when the captured slot power limit value is greater than or equal to this field, the pwr_ok signal is asserted. used when the device capabilities register captured slot power limit scale field is 01b (scale = 0.1x). rw 0h 23:16 power compare 2 specifies the power required for th is device and downstream pci de vices. it is compared with the device capabilities register captured slot power limit value field. when the captured slot power limit value is greater than or equal to this field, the pwr_ok signal is asserted. used when the device capabilities register captured slot power limit scale field is 10b (scale = 0.01x). rw 0h 31:24 power compare 3 specifies the power required for th is device and downstream pci de vices. it is compared with the device capabilities register captured slot power limit value field. when the captured slot power limit value is greater than or equal to this field, the pwr_ok signal is asserted. used when the device capabilities register captured slot power limit scale field is 11b (scale = 0.001x). rw 0h
forward bridge mode configuration registers plx technology, inc. 172 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-73. (offset 1020h; gpioctl) general-purpose i/o control bit(s) description access default 0 gpio0 data when programmed as an output, values writte n to this bit appear on the gpio0 ball. reading this bit returns the value that was previously written. when programmed as an input, reading this b it returns the value present on the gpio0 ball. rw 0 1 gpio1 data when programmed as an output, values writte n to this bit appear on the gpio1 ball. reading this bit returns the value that was previously written. when programmed as an input, reading this b it returns the value present on the gpio1 ball. rw 0 2 gpio2 data when programmed as an output, values writte n to this bit appear on the gpio2 ball. reading this bit returns the value that was previously written. when programmed as an input, reading this b it returns the value present on the gpio2 ball. rw 0 3 gpio3 data when programmed as an output, values writte n to this bit appear on the gpio3 ball. reading this bit returns the value that was previously written. when programmed as an input, reading this b it returns the value present on the gpio3 ball. rw 0 4 gpio0 output enable the gpio diagnostic select field overrides this bit when a diagnostic output is selected. 0 = gpio0 ball is an input 1 = gpio0 ball is an output rw 1 5 gpio1 output enable the gpio diagnostic select field overrides this bit when a diagnostic output is selected. 0 = gpio1 ball is an input 1 = gpio1 ball is an output rw 0 6 gpio2 output enable the gpio diagnostic select field overrides this bit when a diagnostic output is selected. 0 = gpio2 ball is an input 1 = gpio2 ball is an output rw 0 7 gpio3 output enable the gpio diagnostic select field overrides this bit when a diagnostic output is selected. 0 = gpio3 ball is an input 1 = gpio3 ball is an output rw 0 8 gpio0 interrupt enable 1 = changes on the gpio0 ball (when programmed as an input) are enabled to generate an interrupt rw 0 9 gpio1 interrupt enable 1 = changes on the gpio1 ball (when programmed as an input) are enabled to generate an interrupt rw 0 10 gpio2 interrupt enable 1 = changes on the gpio2 ball (when programmed as an input) are enabled to generate an interrupt rw 0 11 gpio3 interrupt enable 1 = changes on the gpio3 ball (when programmed as an input) are enabled to generate an interrupt rw 0
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 173 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 13:12 gpio diagnostic select selects diagnostic signals that are output on the gpio balls. 00b = normal gpio operation 01b = gpio0 driven high when link is up. gpio [3:1] operate according to the configuration specified by bits [7:5] of this register 10b = gpio[3:0] driven with lower four bits of the ltssm state machine for 2 seconds, alternating with gpio[1:0] driven with the uppe r two bits of the ltssm state machine for 1s 11b = gpio[3:0] driven with pmu linkstate (l2, l1, l0s, and l0) ltssm codes 00h ? l3_l2 (fundamental reset) 01h ? detect 02h ? polling.active 03h ? polling.configuration 04h ? polling.compliance 05h ? reserved 06h ? reserved 07h ? reserved 08h ? reserved 09h ? configurati on.linkwidth.start 0ah ? configuration.linkwidth.accept 0bh ? configuration. lanenum.wait & accept 0ch ? configuration.complete 0dh ? configuration.idle 0eh ? l0 0fh ? l0 (transmit e.i.ordered-set) 10h ? l0 (wait e.i.ordered-set) 12h ? l1.idle 14h ? l2.idle 15h ? recovery.rcvrlock (extended sync enabled) 16h ? recovery.rcvrlock 17h ? recovery.rcvrcfg 18h ? recovery.idle 19h ? disabled (transmit ts1) 1ah ? disabled (trans mit e.i.ordered-set) 1dh ? disabled (wa it electrical idle) 1eh ? disabled (disable) 1fh ? loopback.entry 20h ? loopback.active 21h ? loopback.exit 22h ? reserved 23h ? hot reset (reset active) 24h ? loopback.actice (tra nsmit e.i.ordered-set) 25h ? loopback.active (w ait electri cal idle) rw 01b 31:14 reserved rsvdp 0h register 15-73. (offset 1020h; gpioctl) general-purpose i/o control (cont.) bit(s) description access default
forward bridge mode configuration registers plx technology, inc. 174 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-74. (offset 1024h; gpiostat) general-purpose i/o status bit(s) description access default 0 gpio0 interrupt set when the gpio0 ball state ch anges and the ball is programm ed as an input. writing 1 clears this bit. rw1c 0 1 gpio1 interrupt set when the gpio1 ball state ch anges and the ball is programm ed as an input. writing 1 clears this bit. rw1c 0 2 gpio2 interrupt set when the gpio2 ball state ch anges and the ball is programm ed as an input. writing 1 clears this bit. rw1c 0 3 gpio3 interrupt set when the gpio3 ball state ch anges and the ball is programm ed as an input. writing 1 clears this bit. rw1c 0 31:4 reserved rsvdz 0h register 15-75. (offset 1030h; mailbox0) mailbox 0 bit(s) description access default 31:0 mailbox data written or read from the pci express or pci bus. interrupts are generated to the pci express interface or pci bus when this register is written. rw feedfaceh register 15-76. (offset 1034h; mailbox1) mailbox 1 bit(s) description access default 31:0 mailbox data written or read from the pci express or pci bus. interrupts are generated to the pci express interface or pci bus when this register is written. rw 0h register 15-77. (offset 1038h; mailbox2) mailbox 2 bit(s) description access default 31:0 mailbox data written or read from the pci express or pci bu s. interrupts are generated to the pci express interface or pci bus when this register is written. rw 0h register 15-78. (offset 103ch; mailbox3) mailbox 3 bit(s) description access default 31:0 mailbox data written or read from the pci express or pci bu s. interrupts are generated to the pci express interface or pci bus when this register is written. rw 0h
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 175 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 note: chiprev is the silicon revision, encoded as a 4-digit bcd value. the chiprev value for the third release of the chip (rev. bb) is 0201h. the least-significant digit is incremented for mask changes, and the most-significant digit is incremented for major revisions. register 15-79. (offset 1040h; chiprev) chip silicon revision bit(s) description access default 15:0 chip revision returns the pex 8111 current silicon revision number. ro current revision 31:16 reserved rsvdp 0h register 15-80. (offset 1044h; diagctl) diagnostic control ( factory test only ) bit(s) description access default 0 fast times factory test only. rw 0 1 force pci interrupt 1 = forces the pci int x # interrupt signal to assert. the pci interrupt pin register determines which int x # signal is asserted. effective only when the pci command register interrupt disable bit is low. rw 0 2 force pci serr 1 = forces the pci serr# interrupt signal to assert when the bridge control register secondary serr# enable bit is set rw 0 3 force pci express interrupt 1 = forces an interrupt to the pci express ro ot complex, using mess age signaled interrupts or virtual int x # interrupts rw 0 31:4 reserved rsvdp 0h
forward bridge mode configuration registers plx technology, inc. 176 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-81. (offset 1048h; tlpcfg0) tlp controller configuration 0 bit(s) description access default 7:0 cfg_num_fts forced num_fts signal. num_f ts represents the number of fast training sequence (0 to 255). refer to the pci express r1.0a , section 4.2.4.3, fo r detailed information. rw 20h 8 cfg_ack_fmode pci express interface ack_dllp transmitting interval mode. 0 = pci express interface uses own interval value 1 = pci express interface uses cfg_ack_count as interval value rw 0 9 cfg_to_fmode pci express interface timeout de tection mode for replay timer. 0 = pci express interface uses own timer value 1 = pci express interface uses cfg_to_count as timer value rw 0 10 cfg_port_disable 1 = serdes in the pci express in terface is disabled. this allo ws the endpoint to disable the pci express connection when powered up or before the configuration is completed. rw 0 11 cfg_rcv_detect set when the pci express interface establishes the pci express connection. ro 0 12 cfg_lpb_mode link loop-back mode. 1 = pex 8111 changes its ltssm state to the loop- back state, becomes the loop-back master, and starts transmitting pack ets of pseudo random numbers rw 0 13 cfg_port_mode 0 = link pci express interface is confi gured as an upstream port (endpoint) 1 = link pci express interface is configur ed as a downstream port (root complex) rw 0 14 reserved rsvdp 0 15 cfg_ecrc_gen_enable 1 = link is allowe d generate ecrc the pex 8111 does not support ecrc; theref ore, this bit is cleared to 0. rw 0
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 177 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16 tlp_cpld_nosuccess_malform_enable 0 = received completion is retained 1 = completion received when completion timeout expired is treated as a malformed tlp and discarded rw 1 17 scrambler disable 0 = data scrambling is enabled. 1 = data scrambling is disabled. set only when test ing and debugging. rw 0 18 delay link training 0 = link training is allowed to commence immediately after perst# is de-asserted 1 = link training is delayed for 12 ms after perst# is de-asserted when gpio3 is low at the trailing edge of reset , this bit is automatically set. because this bit is used during link training, it must be set by driving gpio3 low during perst# assertion. rw 0 19 decode primary bus number 0 = pex 8111 ignores the primary bus number in a pci express type 0 configuration request. 1 = pex 8111 compares the primary bus number in a pci express type 0 configuration request with the primary bus number register. when they match, the request is accepted. otherwise, an unsupported request is returned. this comparison occurs only after the first type 0 configuration write occurs. rw 0 20 ignore function number 0 = pex 8111 only responds to function number 0 during a type 0 configuration transaction. accesses to other function numbers result in an unsupported request (pci express) or master abort (pci). 1 = pex 8111 ignores the function number in a pci or pci express type 0 configuration request, and responds to all eight functions. rw 0 21 check rcb boundary 0 = pex 8111 ignores read completion boundary (rcb) violations. 1 = pex 8111 checks for rcb violations. when de tected, the pex 8111 treats it as a malformed tlp (packet is dropped and a non-fata l error message is transmitted). rw 0 22 limit completion flow control credit 0 = pex 8111 advertises infinite flow control credits for completions. 1 = pex 8111 advertises completion flow control credits, based on available buffer storage. must be set when the pci control register programmed prefetch size field is set to 4 kb. when gpio2 is low at the trailing edge of perst#, this bit is automatically set. because this bit is used during link training, it must be set by driving gpio2 low during perst# assertion. rw 0 23 l2 secondary bus reset does not apply to forward bridge mode. rw 1 31:24 reserved rsvdp 0h register 15-82. (offset 104ch; tlpcf g1) tlp controller configuration 1 bit(s) description access default 20:0 cfg_to_count pci express interface replay timer timeout value when cfg_to_fmode is set to 1. rw d4h 30:21 cfg_ack_count pci express interface ack dllp transmitting interval value when cfg_ack_fmode is set to 1. rw 0h register 15-81. (offset 1048h; tlpcfg0) tlp controller configuration 0 (cont.) bit(s) description access default
forward bridge mode configuration registers plx technology, inc. 178 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 31 reserved rsvdp 0 register 15-83. (offset 1050h; tlpcfg2) tlp controller configuration 2 bit(s) description access default 15:0 cfg_completer_id0 bits [15:8] = bus number bits [7:3] = device number bits [2:0] = function number the bus, device, and function numbers of a configuration transaction to the pex 8111 are latched in this register. the latched values are then used when generating the completion. rw 0h 26:16 update credit fc controls a counter that determines the gap between updatefc dllps (in units of 62.5 mhz clocks = 16 ns = 4 symbol times). when data or headers are read from the tlp controller, the credit allocation manager tr ansmits a set of updatefc dl lps; posted, non-posted, and completion when the tlp controller configuration 0 register limit completion flow control credit bit is set. while transmitting the set of dllps, the credit allocation manager uses the counter value to in sert gaps between the dllps. the bus, device, and function numbers of a configuration transaction to the pex 8111 are latched in this register. the latched values are then used when generating the completion. rw 1h 31:27 reserved rsvdp 0h register 15-84. (offset 1054h; tlptag) tlp controller tag bit(s) description access default 7:0 tag bme1 message request tag field. rw 0h 15:8 tag erm error manager tag field. rw 0h 23:16 tag pme power manager tag field. rw 0h 31:24 reserved rsvdp 0h register 15-82. (offset 104ch; tlpcf g1) tlp controller configuration 1
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 179 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 15-85. (offset 1058h; tlptimelimit0) tlp controller time limit 0 bit(s) description access default 23:0 bme_completion_timeout_limit bus master engine completion timeout (i n pci clock units). the default value produces a 10-ms timeout. rw 51615h (m66en low) a2c2ah (m66en high) 27:24 l2l3_pwr_removal_time_limit determines length of time before power is removed after entering the l2 state. value to be at least 100 ns. contains pci clock units. rw 4h (m66en low) 8h (m66en high) 31:28 reserved rsvdp 0h register 15-86. (offset 105ch; tlptime limit1) tlp controller time limit 1 bit(s) description access default 10:0 aspm_li_dllp_interval_time_limit determines time interval between two consecutive pm_active_state_request_l1 dllp tr ansmissions. the de fault is 10 s for both 14dh and 29ah. allow at least 10 s spent in ltssm l0 and l0s state before the next pm_active_state_request_l1 dllp is transmitted. refer to the pci express r1.0a errata, page 19, for detailed information. contains pci clock units. rw 14dh (m66en low) 29ah (m66en high) 31:11 reserved rsvdp 0h register 15-87. (offset 1060h; crstimer) crs timer bit(s) description access default 15:0 crs timer valid only when the pci express device control register bridge configuration retry enable bit is set. deter mines the number of microseconds to wait before returning a completion with crs status in response to a pci express-to-pci configuration transaction. when the timer times out and the completion with crs status is returned, the transa ction is discarded from the non-posted transaction queue. rw 25d 31:16 reserved rsvdp 0h register 15-88. (offset 1064h; ecfga ddr) enhanced configuration address bit(s) description access default 11:0 reserved rsvdp 0h 14:12 configuration function number provides the function number for an enhanced configuration transaction. rw 000b 19:15 configuration device number provides the device number for an enhanced configuration transaction. rw 0h 27:20 configuration bus number provides the bus number for an enhanced configuration transaction. rw 0h 30:28 reserved rsvdp 000b 31 enhanced configuration enable does not apply to forward bridge mode. rw 0
forward bridge mode configuration registers plx technology, inc. 180 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 181 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 16 reverse bridge mode configuration registers 16.1 register description this chapter describes the pex 8111 configuration regi sters specific to reverse bridge mode. registers specific to forward bridge mode are discussed in chapter 15 . the pci-compatible reverse bridge mode configur ation registers are accessed by the pci host, using the pci configuration address sp ace. all configuration registers are accessed from the pci express interface or pci bus, using the 64-kb memory space defined by the pci base address 0 register. registers that are written by the serial eeprom controller are also wri tten using memory writes through the pci base address 0 register. in reverse bridge mode, a pci master cannot acce ss the pci express extended capability registers by way of pci configuration transactions. when the configuration regi sters are accessed using memo ry transactions to the pci base address 0 register, the address mapping delineated in table 16-1 is used. the serial eeprom controller writes to configuration registers. an upper address bit is used to select one of two register spaces, as delineated in table 16-2 . each register is 32 bits wide, and is accessed on e byte, word, or dword at a time. these registers utilize little endian byte ordering, which is consistent with the pci r3.0 . the least significant byte in a dword is accessed at address 0. the least significant bit in a dword is 0, and the most significant bit is 31. after the pex 8111 is powered up or reset, the registers are set to their default values. writes to unused registers are ignored, and reads from unused registers return a value of 0. table 16-1. reverse bridge mode pci base address 0 register map address offset register space 0000h - 0fffh pci-compatible configuration registers 1000h - 1fffh main configuration registers 2000h - 2fffh memory-mapped indirect access to downstream pci express endpoint registers 8000h - 9fffh 8-kb internal shared memory table 16-2. selecting register space ad12 register space 0 pci-compatible configuration registers 1 main configuration registers
reverse bridge mode configuration registers plx technology, inc. 182 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.1.1 indexed addressing in addition to me mory-mapped accesses, the pex 8111 main configuration registers can be accessed using the main control register index and main control register data registers. this method allows all main configuration registers to be acces sed using configuration tr ansactions, rather than memory transactions. first, the main configuration register offset is written to the main control register index register (offset 84h). then, the main configuration register is written or read by accessing the main control register data register (offset 88h). 16.2 configuration access types table 16-3 delineates configuration acce ss types referenced by the registers in this chapter. 16.3 register attributes table 16-4 delineates the register attributes used to in dicate access types provided by each register bit. table 16-3. configuration access types access type description cfg initiated by pci configuration transactions on the primary bus. mm initiated by pci memory transactions on the primary or secondary bus, using the address range defined by the pci base address 0 register. ee initiated by the serial eeprom controller during initialization. table 16-4. access provided by register bits register attribute description hwinit hardware initialized register bits are initialized by firmware or hardware mechanisms such a s ball strapping (on the bar0enb# , extarb , and forward balls) or serial eeprom. bits are read-only after initialization and re set only with ?fundamental reset.? ro read-only register register bits are read-only and cannot be altered by software. register bits are initialized by a pex 8111 hardware initia lization mechanism or pex 811 1 serial eeprom register initialization feature. rsvdp reserved and preserved reserved for future rw implementations. register s are read-only and must return 0 when read. software must preserve value read for writes to bits. rsvdz reserved and zero reserved for future rw1c implementations. regi sters are read-only and must return 0 when read. software must use 0 for writes to bits. rw read-write register register bits are read-write and set or cleared by software to the needed state. rw1c read-only status, write 1 to clear status register register bits indicate status when read; a set bit indicating a status event is cleared by writing 1. writing 0 to rw1c bits has no effect. wo write-only used to indicate that a register is written by the serial eeprom controller.
june, 2006 register summary pex 8111bb expresslane pci express-to-pci bridge data book 183 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.4 register summary table 16-5. reverse bridge mode register summary register group pci space address range pci-compatible configuration registers (type 1) pci configuration 00h - 0ffh memory-mapped, bar0 pci express extended capability registers memory-mapped, bar0 100h - 1ffh main control registers memory-mapped, bar0 1000h - 10ffh pci express configuration registers using enhanced configuration access memory-mapped, bar0 2000h - 2fffh 8-kb shared memory instead of general pu rpose memory memory-mapped, bar0 8000h - 9fffh
reverse bridge mode configuration registers plx technology, inc. 184 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.5 register maps 16.5.1 pci-compatible configuration registers (type 1) table 16-6. reverse bridge mode pci-compatible configuration (type 1) register map pci configuration register offset 31 24 23 16 15 8 70 00h pci device id pci vendor id 04h pci status pci command 08h pci class code pci device revision id 0ch pci built-in self-test (not supported) pci header type pci bus latency timer pci cache line size 10h pci base address 0 14h pci base address 1 18h reserved subordinate bus number secondary bus number primary bus number 1ch secondary status i/ o limit i/o base 20h memory limit memory base 24h prefetchable memory limit prefetchable memory base 28h prefetchable memory base upper 32 bits 2ch prefetchable memory limit upper 32 bits 30h i/o limit upper 16 bits i/ o base upper 16 bits 34h reserved pci capabilities pointer 38h pci base address for expansion rom ( not supported ) 3ch bridge control pci interrupt pin pci interrupt line
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 185 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.5.2 pci-compatible exte nded capability registers for pci express interface table 16-7. reverse bridge mode pci-compatible extended capability for pci express interface register map pci configuration register offset 31 24 23 16 15 8 70 40h power management capabilities power management next capability pointer power management capability id 44h power management data power management bridge support power management control/status 48h device-specific control 4ch reserved 50h message signaled interrupts control message signaled interrupts next capability pointer message signaled interrupts capability id 54h message signaled in terrupts address 58h message signaled inte rrupts upper address 5ch reserved message signaled interrupts data 60h pci express capabilities pci express next capability pointer pci express capability id 64h device ca pabilities 68h pci express device status pci express device control 6ch link capabilities 70h link status link control 74h slot capabilities 78h slot status slot control 7ch reserved root control 80h root status 84h main control register index 88h main control register data
reverse bridge mode configuration registers plx technology, inc. 186 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.5.3 pci express extend ed capability registers table 16-8. reverse bridge mode power budgeting ca pability and device serial number register map pci express configuration register offset 31 20 19 16 15 8 70 100h power budgeting next capability offset power budgeting capability ve r s i o n power budgeting pci express extended capability id 104h reserved power budgeting data select 108h power budgeting data 10ch reserved power budget capability 110h serial number next capability offset serial number capability ve r s i o n serial number pci express extended capability id 114h serial number low (lower dword) 118h serial number hi (upper dword)
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 187 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.5.4 main control registers table 16-9. reverse bridge mode 32-bit main control register map pci express configuration register offset 31 0 1000h device initialization 1004h serial eeprom control 1008h serial eeprom clock frequency 100ch pci control 1010h reserved 1014h pci interrupt request enable 1018h interrupt request status 101ch reserved 1020h general-purpose i/o control 1024h general-purpose i/o status 1030h mailbox 0 1034h mailbox 1 1038h mailbox 2 103ch mailbox 3 1040h chip silicon revision 1044h diagnostic control (factory test only) 1048h tlp controller configuration 0 104ch tlp controller configuration 1 1050h tlp controller configuration 2 1054h tlp controller tag 1058h tlp controller time limit 0 105ch tlp controller time limit 1 1060h reserved 1064h enhanced configuration address
reverse bridge mode configuration registers plx technology, inc. 188 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.6 pci-compatible configur ation registers (type 1) register 16-1. (offset 00h; pcivendid) pci vendor id bit(s) description cfg mm ee default 15:0 pci vendor id identifies the pex 8111 manufacturer. the pex 8111 returns the plx pci-sig-assigned vendor id, 10b5h. ro rw wo 10b5h register 16-2. (offset 02h; pcidevid) pci device id bit(s) description cfg mm ee default 15:0 pci device id identifies the particular device, as specified by the vendor. the pex 8111 returns the plx-assigned device id, 8111h. ro rw wo 8111h
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 189 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-3. (offset 04h; pcicmd) pci command bit(s) description cfg mm ee default 0 i/o access enable enables the pex 8111 to respond to i/o space accesses on the primary interface (pci). these accesses are directed to a target on the pci express interface, because the pex 8111 does not have internal i/o-mapped devices. 0 = pci i/o accesses to the pex 8111 result in a master abort rw rw wo 0 1 memory space enable enables the pex 8111 to respond to me mory space accesses on the primary interface (pci). these accesses are directed to a target on the pci express interface, or to internal memory-mapped registers. 0 = pci memory accesses to the pex 8111 result in a master abort rw rw wo 0 2 bus master enable 0 = pex 8111 must disabl e response as a target to all memory or i/o transactions on the pci express se condary interface (they cannot be forwarded to the primary interface). in this case, all memory and i/o requests are terminated with an unsupported request completion. 1 = enables the pex 8111 to perform me mory or i/o transactions on the pci bus. configuration transactions are forwarded from the pci express interface and performed on the pci bus, independent of this bit. rw rw wo 0 3 special cycle enable bridges do not respond to special cycle transactions; therefore, forced to 0. ro ro ? 0 4 memory write and invalidate 0 = enables the pex 8111 pci bus master logic to use the memory write command 1 = enables the pex 8111 pci bus master logic to use the memory write and invalidate command rw rw wo 0 5 vga palette snoop 1 = i/o writes in the first 64 kb of th e i/o address space with address bits [9:0] equal to 3c6h, 3c8h, and 3c9h (i nclusive of isa aliases ? ad[15:10] are not decoded and are of any value) must be positive ly decoded on the pci interface and forwarded to th e pci express secondary interface rw rw wo 0 6 parity error response enable enables pci parity checking. rw rw wo 0 7 reserved rsvdp rsvdp ? 0 8 serr# enable 1 = enables the serr# signal to assert rw rw wo 0 9 fast back-to-back enable the pex 8111 pci master interface doe s not perform fast back-to-back transactions; therefore, forced to 0. ro ro ? 0 10 interrupt disable 1 = pex 8111 is prevented from asserting int x # signals on behalf of functions integrated into the pex 8111 there is no effect on int x # signals asserted on behalf of int x # messages associated with the pci ex press secondary interface. rw rw wo 0 15:11 reserved rsvdp rsvdp ? 0h
reverse bridge mode configuration registers plx technology, inc. 190 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-4. (offset 06h; pcistat) pci status bit(s) description cfg mm ee default 2:0 reserved rsvdz rsvdz ? 000b 3 interrupt status reflects the pex 8111 internal pci inte rrupt status state. one of the int x # signals is asserted when this bit is high, the pci command register interrupt disable bit is low, and the power state is d0. ro ro ? 0 4 capabilities list indicates when the pci capabilities pointer at offset 34h is valid. ro ro ? 1 5 66-mhz capable indicates whether the pex 8111 is capable of running at 66 mhz. 0 = indicates 33 mhz 1 = indicates pex 8111 is 66-mhz capable ro rw wo 1 6 reserved rsvdz rsvdz ? 0 7 fast back-to-back transactions capable the pex 8111 does not accept fast back -to-back transactions; therefore, forced to 0. ro ro ? 0 8 master data parity error 1 = indicates that a data parity error occurred when this device was the pci bus master. the pci command register parity error response enable bit must be set for this bit to be set. writing 1 clears this bit. rw1c rw1c ? 0 10:9 devsel timing determines how quickly this de vice responds to a transaction with devsel#. 01b = indicates a medium response ro ro ? 01b 11 signaled target abort reports target abort termination signaling by the pex 8111 when it responds as the transaction target on its primary interface. this does not occur on the pex 8111; therefore, this bit always returns 0. rsvdz rsvdz ? 0 12 received target abort reports target abort termination dete ction by the pex 8111 when it is the transaction master on its primary interface. writing 1 clears this bit. rw1c rw1c ? 0 13 received master abort reports master abort term ination detection by the pex 8111 when it is the transaction master on its primary interface. writing 1 clears this bit. rw1c rw1c ? 0 14 signaled system error set when the pex 8111 asserts the serr# signal. writing 1 clears this bit. rw1c rw1c ? 0 15 detected parity error set when the pex 8111 detects a parity error on incoming addresses or data from the pci bus, regardless of the pci command register parity error response enable bit state. writing 1 clears this bit. rw1c rw1c ? 0
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 191 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-5. (offset 08h; pcidevrev) pci device revision id bit(s) description cfg mm ee default 7:0 pci device revision id identifies the pex 8111 silicon revision. bi ts [3:0] represent the minor revision number and bits [7:4] repres ent the major revision number. ro ro ? 21h register 16-6. (offset 09h; pciclass) pci class code bit(s) description cfg mm ee default 7:0 programming interface ro rw wo 00h 15:8 subclass code ro rw wo 04h 23:16 base class code ro rw wo 06h
reverse bridge mode configuration registers plx technology, inc. 192 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-7. (offset 0ch; pcicachesize) pci cache line size bit(s) description cfg mm ee default 7:0 pci cache line size specifies the system cache line size (in units of dwords). the value in this register is used by pci master devices to determine whether to use read, memory read line, memory read multiple, or memory write and invalidate commands for accessing memory. the pex 8111 supports cache li ne sizes of 2, 4, 8, 16, or 32 dwords. writes of values other than these result in a cach e line size of 0; however, the value written is returned when this register is read. rw rw wo 0h register 16-8. (offset 0dh; pcilatency) pci bus latency timer bit(s) description cfg mm ee default 7:0 pci bus latency timer also referred to as primary latency timer for type 1 configuration space header devices. specifies (in pci clock units) the value of the latency timer during bus master bursts. when the latency timer expires, the pex 8111 must terminate its tenure on the bus. rw rw wo 0h register 16-9. (offset 0eh; pciheader) pci header type bit(s) description cfg mm ee default 7:0 pci header type specifies the format of the second part of the pre-defined configuration header starting at offset 10h. for pci bri dges, this field is forced to 1h. ro ro ? 1h register 16-10. (offset 0fh; pcibist) pci built-in self-test bit(s) description cfg mm ee default 7:0 pci built-in self-test not supported . always returns a value of 0h. ro ro ? 0h
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 193 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-11. (offset 10h; pcibase0) pci base address 0 bit(s) description cfg mm ee default 0 space type when low, this space is accessed as memory. when high, this space is accessed as i/o. note: hardwired to 0. ro ro ? 0 2:1 address type indicates the type of a ddressing for this space. 00b = locate anywhere in 32-bit address space 01b = locate below 1 mb 10b = locate anywhere in 64-bit address space 11b = reserved ro rw wo 10b 3 prefetch enable 1 = indicates that prefetchi ng has no side effects on reads ro rw wo 1 15:4 base address this section of the base addre ss is ignored for a 64-kb space. note: hardwired to 0. ro ro ? 0h 31:16 base address specifies the upper 16 bits of the 32-bi t starting base address of the 64-kb address space for the pex 8111 configur ation registers and shared memory. rw rw wo 0h register 16-12. (offset 14h; pcibase1) pci base address 1 bit(s) description cfg mm ee default 31:0 base address 1 determines the upper 32 bits of the address when pci base address 0 is configured for 64-bit addressing. rw rw wo 0h
reverse bridge mode configuration registers plx technology, inc. 194 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-13. (offset 18h; primbusnum) primary bus number bit(s) description cfg mm ee default 7:0 primary bus number used to record the bus number of the pci bus segment to which the primary interface of the pex 8111 is connected. rw rw wo 0h register 16-14. (offset 19h; secbusnum) secondary bus number bit(s) description cfg mm ee default 7:0 secondary bus number used to record the bus number of the pci bus segment to which the pex 8111 secondary interfac e is connected. rw rw wo 0h register 16-15. (offset 1ah; subbusnum) subordinate bus number bit(s) description cfg mm ee default 7:0 subordinate bus number used to record the bus number of the highest-numbered pci bus segment behind (or subordinate to) the pex 8111. rw rw wo 0h
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 195 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-16. (offset 1ch; iobase) i/o base bit(s) description cfg mm ee default 3:0 i/o base address capability indicates the type of a ddressing for this space. 0000b = 16-bit i/o address 0001b = 32-bit i/o address all other values are reserved . ro rw wo 0000b 7:4 i/o base determines the starting address at wh ich i/o transactions on the primary interface are forwarded to the secondary interface. the upper four bits of this register correspond to address bits ad[ 15:12]. for address decoding purposes, the pex 8111 assumes that the lower 12 a ddress bits, ad[11:0], of the i/o base address are zero (0h). therefore, the bottom of the defined i/o address range is aligned to a 4-kb address boundary sp ace, and the top is one less than a 4-kb address boundary space. rw rw wo 0h register 16-17. (offset 1dh; iolimit) i/o limit bit(s) description cfg mm ee default 3:0 i/o limit address capability indicates the type of addressing for this space. 0000b = 16-bit i/o address 0001b = 32-bit i/o address all other values are reserved . the value returned in this field is derived from the i/o base register i/o base address capability field. ro ro ? 0000b 7:4 i/o limit determines the i/o space range forwar ded from the primary interface to the secondary interface. the upper four bits of this register correspond to address bits ad[15:12]. for address decoding purposes, the pex 8111 assumes that the lower 12 address bits, ad[11:0], of the i/o limit address are fffh. when there are no i/o addresses on the secondary side of the bridge, the i/o limit field is programmed to a value smaller than the i/o base register i/o base field. in this case, the pex 8111 does not forward i/o transactions from the primary bus to the secondary bus; however, the pex 8111 does forward all i/o transactions from the seconda ry bus to the primary bus. rw rw wo 0h
reverse bridge mode configuration registers plx technology, inc. 196 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-18. (offset 1eh; secstat) secondary status bit(s) description cfg mm ee default 4:0 reserved rsvdz rsvdz ? 0h 5 secondary 66-mhz capable not valid for pci express. indica tes whether the pex 8111 secondary interface is capable of operati ng at 66 mhz. forced to 0. ro ro ? 0 6 reserved rsvdz rsvdz ? 0 7 secondary fast back-to-back transactions capable not valid for pci express. indica tes whether the pex 8111 secondary interface is capable of decoding fast back-to-back transactions when the transactions are from the same master but to different targets. forced to 0. ro ro ? 0 8 secondary master data parity error used to report data parity error de tection by the pex 8111. set when the bridge control register secondary parity er ror response enable bit is set and either of the following two conditions occur: bridge receives a co mpletion marked poisoned on the secondary interface bridge poisons a write request or read comp letion on the secondary interface writing 1 clears this bit. rw1c rw1c ? 0 10:9 secondary devsel timing not valid for pci express. encode s the secondary interface devsel# timing. forced to 00b. ro ro ? 00b 11 secondary signaled target abort set when the pex 8111 completes a reque st as a transaction target on its secondary interface usi ng completer abort completion status. writing 1 clears this bit. rw1c rw1c ? 0 12 secondary received target abort set when the pex 8111 receives a completion with completer abort completion status on its secondary in terface. writing 1 clears this bit. rw1c rw1c ? 0 13 secondary received master abort set when the pex 8111 receives a co mpletion with unsupported request completion status on its secondary in terface. writing 1 clears this bit. rw1c rw1c ? 0 14 secondary received system error set when the pex 8111 receives an err_fatal or err_nonfatal message from the downstream pci expr ess device. writing 1 clears this bit. rw1c rw1c ? 0 15 secondary detected parity error set by the pex 8111 when it receives a poisoned tlp on the secondary interface, regardless of the bridge control register secondary parity error response enable bit state. writing 1 clears this bit. rw1c rw1c ? 0
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 197 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-19. (offset 20h; membase) memory base bit(s) description cfg mm ee default 3:0 reserved note: hardwired to 0h. rsvdp rsvdp ? 0h 15:4 memory base determines the starting address at whic h memory transactions on the primary interface are forwarded to the secondary interface. the upper 12 bits of this register correspond to address bits ad[31:20]. for address decoding purposes, the pex 8111 assumes that the lower 20 address bits, ad[19:0], of the memory base address are zero (0h). the bottom of the defined memory addre ss range is aligned to a 1-mb address boundary space, and the t op is one less than a 1-mb address boundary space. rw rw wo ? register 16-20. (offset 22h; memlimit) memory limit bit(s) description cfg mm ee default 3:0 reserved note: hardwired to 0h. rsvdp rsvdp ? 0h 15:4 memory limit determines the memory space range fo rwarded from the primary interface to the secondary interface. the upper 12 bits of this register correspond to address bits ad[31:20]. for addre ss decoding purposes, the pex 8111 assumes that the lower 20 address bi ts, ad[19:0], of the memory limit address are fffffh. when there are no memory-mapped i/o addresses on the secondary side of the bridge, the memory limit field must be programmed to a value smaller than the memory base register memory base field. when there is no prefetchable memo ry, and no memory-mapped i/o on the secondary side of the bridge, the pex 8111 does not forward memory transactions from the primary bus to the secondary bus; however, it does forward all memory transactions from the secondary bus to the primary bus. rw rw wo ?
reverse bridge mode configuration registers plx technology, inc. 198 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-21. (offset 24h; prebase) prefetchable memory base bit(s) description cfg mm ee default 3:0 prefetchable base address capability indicates the type of addressing for this space. 0000b = 32-bit i/o address 0001b = 64-bit i/o address all other values are reserved . ro rw wo 0000b 15:4 prefetchable memory base determines the starting address at which prefetchable memory transactions on the primary interface are forwarded to th e secondary interface. the upper 12 bits of this register correspond to address bits ad[31:20]. for address decoding purposes, the pex 8111 assumes that the lower 20 address bits, ad[19:0], of the prefetchable memory base address are zero (0h). the bottom of the defined prefetchable memory address range is aligned to a 1-mb address boundary space, and the top is one less than a 1-mb address boundary space. rw rw wo ? register 16-22. (offset 26h; prelimit) prefetchable memory limit bit(s) description cfg mm ee default 3:0 prefetchable limit address capability indicates the type of addressing for this space. 0000b = 32-bit i/o address 0001b = 64-bit i/o address all other values are reserved . the value returned in this field is derived from the prefetchable memory base register prefetchable base address capability field. ro ro ? 0000b 15:4 prefetchable memory limit determines the prefetchable memory space range forwarded from the primary interface to the secondary interface. the up per 12 bits of this register correspond to address bits ad[31:20]. for a ddress decoding purposes, the pex 8111 assumes that the lower 20 address bits, ad[19:0], of the prefetchable memory limit address are fffffh. when there is no prefetchable memory on the secondary side of the bridge, the prefetchable memory limit field must be programmed to a value smaller than the prefetchable memory base register prefetchable memory base field. when there is no prefetchable memory, and no memory-mapped i/o on the secondary side of the bridge, th e pex 8111 does not forward memory transactions from the primary bus to the secondary bus; however, it does forward all memory transactions from the secondary bus to the primary bus. rw rw wo ?
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 199 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-23. (offset 28h; prebaseupper) prefetchable memory base upper 32 bits bit(s) description cfg mm ee default 31:0 prefetchable memory base upper 32 bits when the prefetchable memory base register prefetchable base address capability field indicates 32-bit addressing, this register is read-only and returns 0h. when the prefetchable base address capability field indicates 64-bit addressing, this register determines the upper 32 bits of the starting address at which prefetchable memory transactions on the primary interface are forwarded to the secondary interface. rw rw wo 0h register 16-24. (offset 2ch; prelimitupper) prefetchable memory limit upper 32 bits bit(s) description cfg mm ee default 31:0 prefetchable memory limit upper 32 bits when the prefetchable memory limit register prefetchable limit address capability field indicates 32-bit a ddressing, this regist er is read-only and returns 0h. when the prefetchable limit address capability field indicates 64-bit addressing, this register determines the upper 32 b its of the prefetchable memory range forwarded from the primary interf ace to the secondary interface. rw rw wo 0h register 16-25. (offset 30h; iobaseupper) i/o base upper 16 bits bit(s) description cfg mm ee default 15:0 i/o base upper 16 bits when the i/o base register i/o base address capability field indicates 16-bit addressing, this register is read-only and returns 0h. when the i/o base addr ess capability field indicates 32-bi t addressing, this register determines the upper 16 bits of the starting address at which i/o transactions on the primary interface ar e forwarded to the secondary interface. rw rw wo ? register 16-26. (offset 32h; ioli mitupper) i/o limit upper 16 bits bit(s) description cfg mm ee default 15:0 i/o limit upper 16 bits when the i/o limit register i/o limit address capability field indicates 16-bit addressing, this register is read-only and returns 0h. when the i/o limit address capability field indicates 32-bit addressing, this register determines the upper 16 bits of the i/o range forwarded from the primary interface to the secondary interface. rw rw wo ?
reverse bridge mode configuration registers plx technology, inc. 200 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-27. (offset 34h; pcicapptr) pci capabilities pointer bit(s) description cfg mm ee default 7:0 pci capabilities pointer provides the offset location of the first new capabilities register. ro rw wo 40h 31:8 reserved rsvdp rsvdp ? 0h register 16-28. (offset 3ch; pciintline) pci interrupt line bit(s) description cfg mm ee default 7:0 pci interrupt line indicates to which system interrupt cont roller input the pex 8111 interrupt ball is connected. device drivers and operating systems use this field. rw rw wo 0h register 16-29. (offset 3dh; pciintpin) pci interrupt pin bit(s) description cfg mm ee default 7:0 pci interrupt pin selects which interrupt pin the pex 8111 uses. 1h = inta# ro rw wo 1h
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 201 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-30. (offset 3eh; bridgectl) bridge control bit(s) description cfg mm ee default 0 secondary parity er ror response enable controls the pex 8111?s response to data parity errors forwarded from the primary interface ( such as , a poisoned tlp). 0 = pex 8111 must ignore data parity errors detected and continue standard operation 1 = pex 8111 must take its standard action when a data parity error is detected rw rw wo 0 1 secondary serr# enable no effect in reverse bridge mode . secondary bus error reporting using serr# is controlled by the root control register. rw rw wo 0 2 isa enable modifies the pex 8111?s response to is a i/o addresses that are enabled by the i/o base and i/o limit registers and located in the first 64 kb of the pci i/o address space. 1 = pex 8111 blocks forwarding from primary to secondary of i/o transactions addressing the last 768 by tes in each 1-kb block. in the opposite direction (secondary to primary), i/o transactions are forwarded when they address the last 768 bytes in each 1-kb block. rw rw wo 0 3 vga enable modifies the pex 8111?s response to vga-compatible addresses. when set, the bridge positively decodes and forwards the following accesses on the primary interface to the secondary interface (and, conversely, blocks the forwarding of these addresses from th e secondary to primary interface): memory accesses in the ra nge 000a_0000h to 000b_ffffh i/o address in the first 64 kb of the i/o address space [address[31:16] for pci express are zero (0000h)] and where address[9:0] is in the range of 3b0h to 3bbh or 3c0h to 3dfh (inclusive of isa address aliases ? address[15:10] can be any value and is not used in decoding) when the vga enable bit is set, vga address forwarding is independent of the isa enable bit value, and the i/o address range and memory address ranges defined by the i/o base and i/o limit , memory base and memory limit , and prefetchable memory base and prefetchable memory limit registers. vga address forwarding is qualified by the pci command register i/o access enable and memory space enable bits. 0 = does not forward vga-compatible memory and i/o addresses from the primary to secondary interface (addres ses defined above), unless they are enabled for forwarding by the defi ned i/o and memory address ranges 1 = forwards vga-compatible memo ry and i/o addresses (addresses defined above) from the primary inte rface to the secondary interface (when the i/o access enable and memory space enable bits are set), independent of the i/o and memory address ranges and isa enable bit rw rw wo 0
reverse bridge mode configuration registers plx technology, inc. 202 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 4 vga 16-bit decode enables the pex 8111 to provide 16-bit decoding of the vga i/o address, precluding the decoding of alias addr esses every 1 kb. useful only when bit 3 ( vga enable ) of this register is also set to 1, enabling vga i/o decoding and forwarding by the pex 8111. enables system configuration software to select between 10- and 16-bit i/o address decoding for all vga i/o regist er accesses that are forwarded from primary to secondary, when the vga enable bit is set to 1. 0 = execute 10-bit address decodes on vga i/o accesses 1 = execute 16-bit address decodes on vga i/o accesses rw rw wo 0 5 master abort mode controls the pex 8111?s behavior wh en it receives a master abort termination on the pci bus or an unsupported request on pci express. 0 = do not report master aborts when pci express ur is received: ? return ffff_ffffh to pci bus for reads ? complete non-posted write normally on pci bus (assert trdy#) and discard the write data ? discard posted pci-to-pci express write data when pci transaction terminates with master abort: ? complete non-posted transact ion with unsupported request ? discard posted write data from pci express-to-pci 1 = report master aborts when pci express ur is received: ? complete reads and non-posted writes with pci target abort ? discard posted pci-to-pci express write data when pci transaction terminates with master abort: ? complete non-posted transact ion with unsupported request ? discard posted write data from pci express-to-pci ? transmit err_nonfatal me ssage for posted writes rw rw wo 0 6 secondary bus reset 1 = causes a hot reset to be co mmunicated on the secondary bus. additionally, the pex 8111 secondary bu s interface, and buffers between the two interfaces (primary and seconda ry), must be initialized to their default state. the primary bus interface and conf iguration space registers are not affected by setting this bit. rw rw wo 0 7 fast back-to-back enable not supported . controls bridge ability to generate fast back-to-back transactions to different devices on the secondary interface. ro ro ? 0 register 16-30. (offset 3eh; bridgectl) bridge control (cont.) bit(s) description cfg mm ee default
june, 2006 pci-compatible configuration registers (type 1) pex 8111bb expresslane pci express-to-pci bridge data book 203 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8 primary discard timer selects the number of pci clocks that the pex 8111 waits for a master on the primary interface to repeat a de layed transaction re quest. the counter starts after the completion (pci express completion associated with the delayed transaction request) re aches the head of the pex 8111 downstream queue ( that is , all ordering requirement s are satisfied and the pex 8111 is ready to complete th e delayed transaction with the originating master on the secondary bus). when the originating master does not repeat the transaction before the counter expires, the pex 8111 delete s the delayed transaction from its queue and sets the discard timer status bit. 0 = secondary discard timer counts 2 15 pci clock periods 1 = secondary discard timer counts 2 10 pci clock periods rw rw wo 0 9 secondary discard timer in reverse bridge mode, this bit does not apply and is forced to 0. ro ro ? 0 10 discard timer status set to 1 when the primary discard timer expires and a delayed completion is discarded from a queue within the pex 8111. rw1c rw1c ? 0 11 discard timer serr# enable when set to 1, enables the pex 8 111 to assert serr# on the primary interface when the primary discard timer expires and a delayed transaction is discarded fro m a queue within the pex 8111. 0 = does not assert serr# on the primary interface as a result of the primary discard timer expiration 1 = generates serr# on the primary interface when the primary discard timer expires and a delayed transaction is discarded from a queue within the pex 8111 rw rw wo 0 15:12 reserved rsvdp rsvdp ? 0h register 16-30. (offset 3eh; bridgectl) bridge control (cont.) bit(s) description cfg mm ee default
reverse bridge mode configuration registers plx technology, inc. 204 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.7 pci-compatible extended capability registers for pci express interface register 16-31. (offset 40h; pwrmngid) power management capability id bit(s) description cfg mm ee default 7:0 power management capability id specifies the power mana gement capability id. ro ro ? 01h register 16-32. (offset 41h; pwrmngnext) power management next capability pointer bit(s) description cfg mm ee default 7:0 pci power management ne xt capability pointer points to the first location of the next item in the new capabilities linked list, message signaled interrupts. ro rw wo 50h register 16-33. (offset 42h; pwrmng cap) power management capabilities bit(s) description cfg mm ee default 2:0 pme version default 010b indicates co mpliance with the pci power mgmt. r1.1. ro rw wo 010b 3 pme clock when low, indicates that no pci clock is required to generate pmeout#. when high, indicates that a pci clock is required to generate pmeout#. ro rw wo 0 4 reserved rsvdp rsvdp ? 0 5 device-specific initialization indicates that the pex 8111 requires special initialization following a transition to the d0_uni nitialized stat e before the generic class device driver uses it. ro rw wo 0 8:6 aux current reports the 3.3vaux auxiliary cu rrent requirements for the pci function. when pmeout# generation from d3cold is not supported by the function, must return a value of 000b. ro rw wo 000b 9 d1 support indicates whether the pex 8111 supports the d1 state. ro rw wo 1 10 d2 support indicates whether the pex 8111 supports the d2 state. ro rw wo 0 15:11 pme support default 11001b indicates that th e corresponding pex 8111 port forwards pme messages in the d0, d3hot, and d3cold power states. xxxx1b = assertable from d0 xxx1xb = assertable from d1 xx1xxb = assertable from d2 x1xxxb = assertable from d3hot 1xxxxb = assertable from d3cold ro rw wo 11001b
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 205 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-34. (offset 44h; pwrmngcs r) power management control/status bit(s) description cfg mm ee default 1:0 power state used to determine or change the current power state. 00b = d0 01b = d1 10b = d2 11b = d3hot a transition from state d3 to state d0 causes a hot reset to occur. in states d1 and d2, when the corresponding d1 support and d2 support bits are set, pci memory and i/o accesses are disabled, as well as the pci interrupt; however, configuration cycles are allowed. in state d3hot, these functions are also disabled. rw rw wo 00b 7:2 reserved rsvdp rsvdp ? 0h 8 pme enable enables the pmeout# signal to assert. rw rw wo 0 12:9 data select not supported. always returns a value of 0h. ro ro ? 0h 14:13 data scale not supported. always returns a value of 00b. ro ro ? 00b 15 pme status when the pme enable bit is set high, indicate s that pmeout# is being driven. writing 1 from the pci bus clears this bit. rw1c rw1c ? 0 register 16-35. (offset 46h; pwrmngbridge) power management bridge support bit(s) description cfg mm ee default 5:0 reserved rsvdp rsvdp ? 0h 6 b2/b3 support 0 = indicates that, when the pex 8111 function is programmed to d3hot, power is removed (b3) from its secondar y bus. useful only when bit 7 is set. 1 = indicates that, when the pex 8111 function is programmed to d3hot, its secondary bus pci clock is stopped (b2). ro rw wo 0 7 bus power/clock control enable 1 = indicates that the bus power/clock control mechanism (as defined in the pci-to-pci bridge r1.1 , section 4.7.1) is enabled ro rw wo 0 register 16-36. (offset 47h; pw rmngdata) power management data bit(s) description cfg mm ee default 7:0 power management data not supported. always returns a value of 0h. ro ro ? 0h
reverse bridge mode configuration registers plx technology, inc. 206 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-37. (offset 48h; d evspecctl) device-specific control bit(s) description cfg mm ee default 0 blind prefetch enable 0 = memory read command on the pci bus that targets the pci express memory space causes only 1 word to be read from the pci express interface. 1 = memory read command on the pci bus that targets the pci express memory space causes at least one cache line to be read from the pci express interface. additional dwor ds can be read by setting the pci control register programmed prefetch size field. rw rw wo 0 1 pci base address 0 enable 1 = enables the pci base address 0 space for memory-mapped access to the configuration registers and shared memory. pci base address 0 is also enabled when the bar0enb# ball is low. rw rw wo 0 2 l2 enable 0 = power state change to d3 does not cause the pex 8111 to change the link state to l2 1 = power state change to d3 causes the pex 8111 to change the link state to l2 rw rw wo 0 3 pmu power off 1 = link transitioned to the l2/l3 rea dy state, and is ready to power down ro ro ? 0 7:4 pmu link state indicates the link state. 0001b = l0 0010b = l0s 0100b = l1 1000b = l2 all other values are reserved . ro ro ? ? 9:8 crs retry control determines the pex 8111 response when a pci-to-pci express configuration transaction is termin ated with a configuration request retry status. 00b = retry once after 1s. when another crs is received, target abort on the pci bus. 01b = retry eight times, one time per second. when anothe r crs is received, target abort on the pci bus. 10b = retry one time per seco nd until successf ul completion. 11b = reserved rw rw wo 00b 10 wake out enable does not apply to reverse bridge mode. rw rw wo 0 11 beacon generate enable does not apply to reverse bridge mode. rw rw wo 0 12 beacon detect enable 1 = beacon detected while the link is in the l2 state causes the power management control/status register pme status bit to be set rw rw wo 0 13 pll locked high when the internal pll is locked. ro ro ? ? 15:14 reserved rsvdp rsvdp ? 00b 20:16 link training and status state machine factory test only. ro ro ? ? 31:21 reserved rsvdp rsvdp ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 207 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-38. (offset 50h; msiid) message signaled interrupts capability id bit(s) description cfg mm ee default 7:0 msi capability id specifies the message signale d interrupts capability id. ro ro ? 5h register 16-39. (offset 51h; msinext) message signaled interrupts next capability pointer bit(s) description cfg mm ee default 7:0 msi next capability pointer points to the first location of the next item in the new capabilities linked list, pci express capability. ro rw wo 60h register 16-40. (offset 52h; msictl) message signaled interrupts control bit(s) description cfg mm ee default 0 msi enable when set: enables the pex 8111 to use msi to request service int x # outputs are disabled rw rw wo 0 3:1 multiple message capable system software reads this field to determine the num ber of requested messages. the number of requested me ssages must be aligned to a power of two (when a function requires th ree messages, it requests four). value number of messages requested 000b 1 001b 2 010b 4 011b 8 100b 16 101b 32 110b, 111b reserved ro ro ? 000b 6:4 multiple message enable system software writes to this fiel d to indicate the number of allocated messages (equal to or less than the number of requested messages). the number of allocated messages is aligned to a power of two. value number of messages requested 000b 1 001b 2 010b 4 011b 8 100b 16 101b 32 110b, 111b reserved rw rw wo 000b 7 msi 64-bit address capable 1 = pex 8111 is capable of gene rating a 64-bit message address ro rw wo 0 8 per vector masking capable not supported. forced to 0. ro ro ? 0 15:9 reserved rsvdp rsvdp ? 0h
reverse bridge mode configuration registers plx technology, inc. 208 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-41. (offset 54h; msiaddr) message signaled interrupts address bit(s) description cfg mm ee default 1:0 reserved rsvdp rsvdp ? 00b 31:2 msi address when the message signaled interrupts control register msi enable bit is set, the register contents specify the dword-aligned address for the msi memory write transaction. address bits [1:0] are driven to zero (00b) during the address phase. rw rw wo 0h register 16-42. (offset 58h; msiupperaddr) message signaled inte rrupts upper address bit(s) description cfg mm ee default 31:0 msi upper address optionally implemented only when the pex 8111 supports a 64-bit message address when the message signaled interrupts control register msi 64-bit address capable bit is set. when the message signaled interrupts control register msi enable bit is set, the register contents specify th e upper 32 bits of a 64-bit message. when the register contents are zero (0h), the pex 8111 uses the 32-bit address specified by the message signaled interrupts address register. rw rw wo 0h register 16-43. (offset 5ch; msidata) message signaled interrupts data bit(s) description cfg mm ee default 15:0 msi data when the message signaled interrupts control register msi enable bit is set, the message data is driven onto the lower word of the ad bus (ad[15:0]) of the memory write transaction da ta phase. the upper word (ad[31:16]) is always cleared to 0h. rw rw wo 0h 31:16 reserved rsvdp rsvdp ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 209 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-44. (offset 60h; pciexid) pci express capability id bit(s) description cfg mm ee default 7:0 pci express capability id specifies the pci express capability id. ro rw ? 10h register 16-45. (offset 61h; pciexnext) pci express next capability pointer bit(s) description cfg mm ee default 7:0 pci express next capability pointer points to the first location of the next item in the new capabilities linked list. ro rw wo 0h register 16-46. (offset 62h; pciexcap) pci express capabilities bit(s) description cfg mm ee default 3:0 capability version indicates the pci express capabi lity structure version number. ro rw wo 1h 7:4 device/port type indicates the type of pc i express logical device. 0000b = pci express endpoint device 0001b = legacy pci express endpoint device 0100b = root port of pci express root complex 0101b = upstream port of pci express switch 0110b = downstream port of pci express switch 0111b = pci express-to-pci/pci-x bridge 1000b = pci/pci-x-to-pci express bridge all other values are reserved . ro rw wo 1000b 8 slot implemented 1 = indicates that the pci express link associated with this port is connected to a slot ro rw wo 0 13:9 interrupt message number when this function is allocated more than one msi interrupt number, this field must contai n the offset between the base message data and the msi message generated when slot status or root status register status bits of this capability structure are set. for the field to be correct, hardware must update it when the number of msi messages assi gned to the pex 8111 changes. ro ro ? 0h 15:14 reserved rsvdp rsvdp ? 00b
reverse bridge mode configuration registers plx technology, inc. 210 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-47. (offset 64h; devcap) device capabilities bit(s) description cfg mm ee default 2:0 maximum payload size supported indicates the maximum pa yload size that the pex 8111 supports for tlps. 000b = 128 bytes all other values are reserved . note: because the pex 8111 supports a maximum payload size of only 128 bytes, this field is hardwired to 000b. ro ro ? 000b 4:3 phantom functions supported not supported. hardwired to 00b. this field indicates support for th e use of unclaimed function numbers to extend the number of outstanding tran sactions allowed, by logically combining unclaimed function numb ers (called phantom functions) with the tag identifier. ro ro ? 00b 5 extended tag field supported indicates the maximum supported size of the tag field. 0 = 5-bit tag field is supported 1 = 8-bit tag field is supported note: 8-bit tag field support must be enabled by the corresponding control field in the pci express device control register. ro rw wo 0 8:6 endpoint l0s acceptable latency indicates the acceptable total latency th at an endpoint withstands due to the transition from the l0s state to the l0 state. it is essentially an indirect measure of the endpoint internal buffering. power management software uses th e reported l0s acceptable latency number to compare against the l0s exit latencies reported by all components comprising the data path from this endpoint to the root complex root port, to determine whether active state li nk pm l0s entry is used with no performance loss. 000b = less than 64 ns 001b = 64 ns to less than 128 ns 010b = 128 ns to less than 256 ns 011b = 256 ns to less than 512 ns 100b = 512 ns to 1 s 101b = 1 s to less than 2 s 110b = 2 to 4 s 111b = more than 4 s ro rw wo 000b
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 211 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 11:9 endpoint l1 acceptable latency indicates the acceptable total latency th at an endpoint withstands due to the transition from the l1 state to the l0 state. it is essentially an indirect measure of the endpoint internal buffering. power management software uses the report l1 acceptable latency number to compare against the l1 exit la tencies reported by all components comprising the data path from this endpoint to the root complex root port, to determine whether active state link pm l1 entry is used with performance loss. 000b = less than 1 s 001b = 1 s to less than 2 s 010b = 2 s to less than 4 s 011b = 4 s to less than 8 s 100b = 8 s to less than 16 s 101b = 16 s to less than 32 s 110b = 32 to 64 s 111b = more than 64 s ro rw wo 000b 12 attention button present not supported. forced to 0. ro ro ? 0 13 attention indicator present. not supported. forced to 0. ro ro ? 0 14 power indicator present not supported. forced to 0. ro ro ? 0 17:15 reserved rsvdp rsvdp ? 000b 25:18 captured slot power limit value specifies the upper limit on power s upplied by slot in combination with the slot power limit scale value. power limit (in watts) is calculated by multiplying the value in this field by the value in the slot power limit scale field. value is set by the set slot power limit message. ro rw wo 0h 27:26 captured slot power limit scale specifies the scale used for the slot power limit value. value is set by the set slot power limit message. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x ro rw wo 00b 31:28 reserved rsvdp rsvdp ? 0h register 16-47. (offset 64h; devcap) device capabilities (cont.) bit(s) description cfg mm ee default
reverse bridge mode configuration registers plx technology, inc. 212 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-48. (offset 68h; devctl) pci express device control bit(s) description cfg mm ee default 0 correctable error reporting enable does not apply to reverse bridge mode. rw rw wo 0 1 non-fatal error reporting enable does not apply to reverse bridge mode. rw rw wo 0 2 fatal error reporting enable does not apply to reverse bridge mode. rw rw wo 0 3 unsupported request reporting enable does not apply to reverse bridge mode. rw rw wo 0 4 enable relaxed ordering not supported . forced to 0. 1 = pex 8111 is permitted to set the relaxe d ordering bit in the attributes field of transactions it initiates that do not require strong write ordering ro ro ? 0 7:5 maximum payload size sets the maximum tlp payload size for the pex 8111. as a receiver, the pex 8111 must handle tlps as large as the set value; as transmitter, the pex 8111 must not generate tlps exceeding the set va lue. permissible values for transmitted tlps are indicated in the device capabilities register maximum payload size supported field. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = reserved rw rw wo 000b
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 213 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 8 extended tag field enable 0 = pex 8111 is restricted to a 5-bit tag field 1 = enables pex 8111 to use an 8-bit tag field as a requester forced to 0 when the device capabilities register extended tag field supported bit is cleared. rw rw wo 0 9 phantom function enable not supported. hardwired to 0. ro ro ? 0 10 auxiliary (aux) power pm enable not supported. hardwired to 0. 1 = enables a device to draw aux power independent of pme aux power devices that require aux power on lega cy operating systems must continue to indicate pme aux powe r requirements. aux po wer is allocated as requested in the power management capabilities register aux current field, independent of the power management control/status register pme enable bit. ro ro ? 0 11 enable no snoop not supported. hardwired to 0. 1 = pex 8111 is permitted to set the no snoop bit in the requester attributes of transactions it initiates that do not require hardware-enforced cache coherency setting this bit to 1 does not ca use a device to blindly set the no snoop attribute on all transactions that it initiates. although th is bit is set to 1, a device only sets the no snoop attribute on a transaction when it can guarantee that the transaction address is not stored in a system cache. the pex 8111 never sets the no snoop attribute; therefore, this bit is forced to 0. ro ro ? 0 14:12 maximum read request size the value specified in this register is the upper boundary of the pci control register programmed prefetch size field if the device-specific control register blind prefetch enable bit is set. sets the maximum read request si ze for the pex 8111 as a requester. the pex 8111 must not generate read re quests with a size that exceeds the set value. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = reserved rw rw wo 010b 15 bridge configuration retry enable 0 = pex 8111 does not generate completi ons with completion retry status on behalf of pci express-to-pci configuration transactions 1 = pex 8111 generates comp letions with completion retry status on behalf of pci express-to-pci configuration transactions rw rw wo 0 register 16-48. (offset 68h; devctl) pci express device control (cont.) bit(s) description cfg mm ee default
reverse bridge mode configuration registers plx technology, inc. 214 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-49. (offset 6ah; devstat) pci express device status bit(s) description cfg mm ee default 0 correctable error detected does not apply to reverse bridge mode. rw1c rw1c ? 0 1 non-fatal error detected does not apply to reverse bridge mode. rw1c rw1c ? 0 2 fatal error detected does not apply to reverse bridge mode. rw1c rw1c ? 0 3 unsupported request detected does not apply to reverse bridge mode. rw1c rw1c ? 0 4 aux power detected devices that require aux power repor t this bit as set when the pex 8111 detects aux power. ro ro ? 0 5 transactions pending because the pex 8111 does not internally generate non-posted transactions, this bit is forced to 0. ro ro ? 0 15:6 reserved rsvdz rsvdz ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 215 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-50. (offset 6ch; linkcap) link capabilities bit(s) description cfg mm ee default 3:0 maximum link speed indicates the maximum link speed of the given pci express link. set to 0001b for 2.5 gbps. all other values are reserved . ro ro ? 0001b 9:4 maximum link width indicates the maximum width of the give n pci express link. by default, the pex 8111 has an x1 link; therefore, th is field is hardwired to 00_0001b. all other values are not supported . ro ro ? 00_0001b 11:10 active state link pm support indicates the level of active state po wer management suppor ted on the given pci express link. 01b = l0s entry supported 11b = l0s and l1 supported 00b, 10b = reserved ro rw wo 11b 14:12 l0s exit latency indicates the l0s exit latency for th e given pci express link. the value reported indicates the length of time this port requires to complete transition from l0s to l0. 000b = less than 64 ns 001b = 64 ns to less than 128 ns 010b = 128 ns to less than 256 ns 011b = 256 ns to less than 512 ns 100b = 512 ns to 1 s 101b = 1 s to less than 2 s 110b = 2 to 4 s 111b = more than 4 s ro rw wo 100b 17:15 l1 exit latency indicates the l1 exit latency for th e given pci express link. the value reported indicates the length of time this port requires to complete transition from l1 to l0. 000b = less than 1 s 001b = 1 s to less than 2 s 010b = 2 s to less than 4 s 011b = 4 s to less than 8 s 100b = 8 s to less than 16 s 101b = 16 s to less than 32 s 110b = 32 to 64 s 111b = more than 64 s ro rw wo 100b 23:18 reserved rsvdp rsvdp ? 0h 31:24 port number indicates the pci express port number for the given pci express link. ro rw wo 0h
reverse bridge mode configuration registers plx technology, inc. 216 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-51. (offset 70h; linkctl) link control bit(s) description cfg mm ee default 1:0 active state link pm control controls the level of active state pm supported on the given pci express link. 00b = disabled 01b = l0s entry supported 10b = reserved 11b = l0s and l1 entry supported note: ?l0s entry enabled? indi cates the transmitter entering l0s. rw rw wo 00b 2 reserved rsvdp rsvdp ? 0 3 read completion boundary (rcb) control 0 = read completion boundary is 64 bytes 1 = read completion boundary is 128 bytes ro rw wo 0 4 link disable disables the link when set to 1. writes to this bit are immediately reflected in the value read from the bit, regardless of actual link state. rw rw wo 0 5 retrain link 1 = initiates link retraining always returns 0 when read. rw rw wo 0 6 common clock configuration 0 = indicates that the pex 811 1 and the component at the opposite end of the link are operating with asynchronous reference clock. components utilize this common clock configuration information to report the correct l0s and l1 exit latencies. 1 = indicates that the pex 811 1 and the component at the opposite end of the link are operating with a distributed common reference clock. rw rw wo 0 7 extended sync 1 = forces extended transmission of fts ordered sets in fts and extra ts2 at exit from l1 prior to entering l0. this mode provides external devices moni toring the link time to achieve bit and symbol lock before th e link enters the l0 state and resumes communication. rw rw wo 0 15:8 reserved rsvdp rsvdp ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 217 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-52. (offset 72h; linkstat) link status bit(s) description cfg mm ee default 3:0 link speed indicates the negotiated link speed of the given pci express link. set to 0001b for 2.5 gbps. all other values are reserved . ro ro ? 0001b 9:4 negotiated link width indicates the negotiated width of the gi ven pci express link. by default, the pex 8111 has an x1 link; therefore, this field is hardwired to 00_0001b. all other values are not supported . ro ro ? 00_0001b 10 link training error indicates that a link training error occurred. cleared by hardware upon successful training of th e link to the l0 state. ro ro ? 0 11 link training indicates that link training is in progress; hardware clears this bit after link training is complete. ro ro ? 0 12 slot clock configuration indicates that the pex 8111 uses the sa me physical reference clock that the platform provides on the connector. when the pex 8111 uses an independent clock irresp ective of the presence of a reference on the connector, this bit must be cleared. hwinit rw wo 0 15:13 reserved rsvdz rsvdz ? 000b
reverse bridge mode configuration registers plx technology, inc. 218 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-53. (offset 74h; slotcap) slot capabilities bit(s) description cfg mm ee default 0 attention button present not supported . forced to 0. ro ro ? 0 1 power controller present not supported . forced to 0. ro ro ? 0 2 mrl sensor present not supported . forced to 0. ro ro ? 0 3 attention indicator present not supported . forced to 0. ro ro ? 0 4 power indicator present not supported . forced to 0. ro ro ? 0 5 hot plug surprise not supported . forced to 0. ro ro ? 0 6 hot plug capable not supported . the pex 8111 does not support hot plug operations; therefore, this bit is forced to 0. ro ro ? 0 14:7 slot power limit value in combination with the slot power limit scale value, specifies the upper limit on power supplied by the slot. the powe r limit (in watts) is calculated by multiplying the value in this field by the value in the slot power limit scale field. writes to this register cause th e pex 8111 to transmit the set slot power limit message downstream. ro rw wo 25d 16:15 slot power limit scale specifies the scale used for the slot power limit value . writes to this register cause the pex 8111 to transmit the set slot power limit message downstream. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x ro rw wo 00b 18:17 reserved rsvdp rsvdp ? 00b 31:19 physical slot number not supported. forced to 0h. ro ro ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 219 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-54. (offset 78h; slotctl) slot control bit(s) description cfg mm ee default 0 attention button pressed enable not supported . forced to 0. rw rw wo 0 1 power fault detected enable not supported . forced to 0. rw rw wo 0 2 mrl sensor changed enable not supported . forced to 0. rw rw wo 0 3 presence detect changed enable not supported . forced to 0. rw rw wo 0 4 command completed interrupt enable not supported . forced to 0. rw rw wo 0 5 hot plug interrupt enable not supported . forced to 0. rw rw wo 0 7:6 attention indicator control not supported . forced to 0. rw rw wo 00b 9:8 power indicator control not supported . forced to 00b. rw rw wo 00b 10 power controller control not supported . forced to 0. rw rw wo 0 15:11 reserved rsvdp rsvdp ? 0h register 16-55. (offset 7a h; slotstat) slot status bit(s) description cfg mm ee default 0 attention button pressed not supported . forced to 0. ro ro ? 0 1 power fault detected not supported . forced to 0. ro ro ? 0 2 mrl sensor changed not supported . forced to 0. ro ro ? 0 3 presence detect changed not supported . forced to 0. ro ro ? 0 4 command completed not supported . forced to 0. ro ro ? 0 5 mrl sensor state not supported . forced to 0. ro ro ? 0 6 presence detect state not supported . forced to 1. ro ro ? 1 15:7 reserved rsvdp rsvdp ? 0h
reverse bridge mode configuration registers plx technology, inc. 220 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-56. (offset 7ch; rootctl) root control bit(s) description cfg mm ee default 0 system error on correctable error enable 1 = system error (serr#) is generated when an err_cor is reported by devices in the hierarchy associated with this root port, or by the root port itself rw rw wo 0 1 system error on non-fatal error enable 1 = system error (serr#) is ge nerated when an err_nonfatal is reported by devices in the hierarchy associated with this root port, or by the root port itself rw rw wo 0 2 system error on fatal error enable 1 = system error (serr#) is generated when an err_fatal is reported by devices in the hierarchy associated with this root port, or by the root port itself rw rw wo 0 3 pme interrupt enable 1 = enables pme interrupt generation upon pme messag e receipt as reflected in the root status register pme status bit. a pme interrupt is also generated when the pme status bit is set when this bit is set from a cleared state. rw rw wo 0 31:4 reserved rsvdp rsvdp ? 0h register 16-57. (offset 80h; rootstat) root status bit(s) description cfg mm ee default 15:0 pme requester id indicates the pci requester id of the last pme requester. ro ro ? ? 16 pme status indicates that pme was asserted by the requester id indicated in the pme requester id field. subsequent pmes remain pending until this bit is cleared by software, by writing 1. rw1c rw1c ? 0 17 pme pending indicates that another pme is pending when the pme status bit is set. when the pme status bit is cleared by software , the pme is delivered by hardware by setting the pme status bit again and updating the requester id appropriately. cleared by hardware when no other pmes are pending. ro ro ? ? 31:18 reserved rsvdp rsvdp ? 0h
june, 2006 pci-compat ible extended capability regist ers for pci express interface pex 8111bb expresslane pci express-to-pci bridge data book 221 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-58. (offset 84h; mainindex) main control register index bit(s) description cfg mm ee default 11:0 main control register index selects a main control register that is accessed by way of the main control register data register. rw rw wo 0h 31:12 reserved rsvdp rsvdp ? 0h register 16-59. (offset 88h; maindata) main control register data bit(s) description cfg mm ee default 31:0 main control register data writes to and reads from this register are mapped to a main control register selected by the main control register index register. rw rw wo 0h
reverse bridge mode configuration registers plx technology, inc. 222 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.8 pci express extended capability registers 16.8.1 pci express power budgeting registers register 16-60. (offset 100h; pwrcaphdr) power budgeting capability header bit(s) description cfg mm ee default 15:0 pci express extended capability id pci-sig-defined id number that indi cates the nature and format of the extended capability. ro rw wo 4h 19:16 capability version pci-sig-defined version number that indicates the version of the capability structure present. ro rw wo 1h 31:20 next capability offset contains the offset to the next pci e xpress capability structure, or 000h when no other items exist in the new capabilities linked list. set to 110h when serial number capability must be enabled. ro rw wo 000h register 16-61. (offset 104h; pwrdatasel) power budgeting data select bit(s) description cfg mm ee default 7:0 data select register indexes the power budgeting data reported through the power budgeting data register. selects the dword of powe r budgeting data that is to appear in the power budgeting data register. the pex 8111 supports values from 0 to 31 for this field. for values greater than 31, a value of 0h is returned when the power budgeting data register is read. rw rw wo 0h 31:8 reserved rsvdp rsvdp ? 0h
june, 2006 pci express power budgeting registers pex 8111bb expresslane pci express-to-pci bridge data book 223 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-62 returns the dword of power budgeting data selected by the power budgeting data select register. when the power budgeting data select register contains a valu e greater than or equal to the number of operating conditions for which the pe x 8111 provides power information, this register returns all zeros (0). the pex 8111 supports 32 operating conditions. register 16-62. (offset 108h; pwrdata) power budgeting data bit(s) description cfg mm ee default 7:0 base power specifies (in watts) the base power value in the given operating condition. this value must be multiplied by the data scale , to produce the actual power consumption value. ro rw wo 0h 9:8 data scale specifies the scale to apply to the base power value. the pex 8111 power consumption is determin ed by multiplying the base power field contents with the value corresponding to the encoding returned by this field. 00b = 1.0x 10b = 0.01x 01b = 0.1x 11b = 0.001x ro rw wo 00b 12:10 pm sub-state specifies the power management s ub-state of the operating condition being described. 000b = default sub-state all other values = devi ce-specific sub-state ro rw wo 000b 14:13 pm state specifies the power management st ate of the operating condition being described. a device returns 11b in this field and aux or pme aux in the pm type field to specify the d3cold pm state. an encoding of 11b along with any other pm type field value specifies the d3hot state. 00b = d0 10b = d2 01b = d1 11b = d3 ro rw wo 00b 17:15 pm type specifies the type of opera ting condition be ing described. 000b = pme aux 011b = sustained 001b = auxiliary 111b = maximum 010b = idle all other values = reserved ro rw wo 000b 20:18 power rail specifies the power rail of the operating condition being described. 000b = power (12v) 111b = thermal 001b = power (3.3v) all other values = reserved 010b = power (1.8v) ro rw wo 000b 31:21 reserved rsvdp rsvdp ? 0h register 16-63. (offset 10ch; pw rbudcap) power budget capability bit(s) description cfg mm ee default 0 system allocated 1 = indicates that the pex 8111 power b udget is included within the system power budget, and software is to ig nore reported power budgeting data for power budgeting decisions ro rw wo 0 31:1 reserved rsvdp rsvdp ? 0h
reverse bridge mode configuration registers plx technology, inc. 224 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.8.2 pci express serial number registers register 16-64. (offset 110h; sercaphdr) serial number capability header bit(s) description cfg mm ee default 15:0 pci express extended capability id pci-sig-defined id number that indi cates the nature and format of the extended capability. forced to 0 when serial number capability is disabled. ro ro ? 3h 19:16 capability version pci-sig-defined version number that indicates the version of the capability structure present. forced to 0h when se rial number capability is disabled. ro ro ? 1h 31:20 next capability offset contains the offset to the next pci e xpress capability st ructure or 000h when no other items exist in the ne w capabilities linked list. ro ro ? 000h register 16-65. (offset 114h; sernumlow) serial number low (lower dword) bit(s) description cfg mm ee default 31:0 pci express device serial number contains the lower dword of the ieee-defined 64-bit extended unique identifier. includes a 24-bit company id value assigned by the ieee registration authority a nd a 40-bit extension identifier assigned by the manufacturer. forced to 0h when se rial number capability is disabled. ro rw wo 0h register 16-66. (offset 118h; sernumhi) serial number hi (upper dword) bit(s) description cfg mm ee default 31:0 pci express device serial number contains the upper dword of the ie ee defined 64-bi t extended unique identifier. includes a 24-bit company id value assigned by the ieee registration authority a nd a 40-bit extension identifier assigned by the manufacturer. forced to 0h when se rial number capability is disabled. ro rw wo 0h
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 225 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16.9 main control registers register 16-67. (offset 1000h; devinit) device initialization bit(s) description cfg mm 3:0 pclko clock frequency controls the pclko ball frequency. when cleared to 0000b, the clock is stopped and remains at a logic low (0v) dc value. non-zero values represent divisors of the 100-mhz refclk. the default value is 0011b, representing a frequency of 66 mhz. 0000b = 0 0001b = 100 0010b = 50 0011b = 33.3/66 (when m66en is hi gh, pclko frequency is 66 mhz) 0100b = 25 0101b = 20 0110b = 16.7 0111b = 14.3 1000b = 12.5 1001b = 11.1 1010b = 10 1011b = 9.1 1100b = 8.3 1101b = 7.7 1110b = 7.1 1111b = 6.7 rw 0011b 4 pci express enable does not apply to reverse bridge mode. rw 0 5 pci enable 0 = all pci accesses to the pex 8111 re sult in a target retry response 1 = pex 8111 responds normally to pci accesses automatically set when a valid serial eeprom is not detected. rw 0 31:6 reserved rsvdp 0h
reverse bridge mode configuration registers plx technology, inc. 226 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-68. (offset 1004h; eectl) serial eeprom control bit(s) description cfg mm 7:0 serial eeprom write data determines the byte written to the serial eeprom when the serial eeprom by te write start bit is set. represents an op code, address, or data being written to the serial eeprom. rw 0h 15:8 serial eeprom read data determines the byte read from the serial eeprom when the serial eeprom by te read start bit is set. ro ? 16 serial eeprom byte write start 1 = value in the serial eeprom write data field is written to the serial eeprom automatically cleared when the write operation is complete. rw 0 17 serial eeprom byte read start 1 = a byte is read from the serial eeprom, and accessed using the serial eeprom read data field automatically cleared when the read operation is complete. rw 0 18 serial eeprom chip select enable 1 = serial eeprom chip select is enabled rw 0 19 serial eeprom busy 1 = serial eeprom controll er is busy performing a byte read or write operation an interrupt is generated when this bit goes false. ro 0 20 serial eeprom valid 1 = serial eeprom with 5ah in the first byte is detected ro ? 21 serial eeprom present set when the serial eeprom cont roller determines that a serial eeprom is connected to the pex 8111. ro ? 22 serial eeprom chip select active set when the eecs# ball to the serial eeprom is active. the chip select can be active across multiple byte operations. ro ? 24:23 serial eeprom address width reports the installed serial ee prom?s addressing width. when the addressing width cannot be determined, 00b is returned. a non-zero value is reported only when the validation signature ( 5ah ) is successfully read from the first serial eeprom location. 00b = undetermined 01b = 1 byte 10b = 2 bytes 11b = 3 bytes ro ? 30:25 reserved rsvdp 0h 31 serial eeprom reload writing 1 to this bit causes the serial eeprom controller to perform an initialization sequence. configuration registers and shared memo ry are loaded from the serial eeprom. reading this bit returns 0 while initialization is in progress, and 1 when initialization is complete. rw 0
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 227 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-69. (offset 1008h; eeclk freq) serial eeprom clock frequency bit(s) description access default 2:0 serial eeprom clock frequency controls the eeclk ball frequency. 000b = 2 mhz 001b = 5 mhz 010b = 8.3 mhz 011b = 10 mhz 100b = 12.5 mhz 101b = 16.7 mhz 110b = 25 mhz 111b = reserved rw 000b 31:3 reserved rsvdp 0h
reverse bridge mode configuration registers plx technology, inc. 228 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-70. (offset 100ch; pcictl) pci control bit(s) description access default 0 pci multi-level arbiter 0 = all pci requesters are placed into a singl e-level round-robin arbiter, each with equal access to the pci bus 1 = two-level arbiter is selected rw 0 3:1 pci arbiter park select determines which pci master controller is granted the pci bus when there are no pending requests. 000b = last grantee 001b = pci express interface 010b, 011b = reserved 100b = external requester 0 101b = external requester 1 110b = external requester 2 111b = external requester 3 rw 000b 4 bridge mode reflects the forward ball status. when low, the pex 8111 operates as a reverse bridge (pci-to-pci express). when high, the pex 8111 operates as a fo rward bridge (pci express-to-pci). ro ? 5 pci external arbiter reflects the extarb ball state. when low, the pex 8111 enables its internal ar biter. it then expect s external requests on req[3:0]# and issues bu s grants on gnt[3:0]#. when high, the pex 8111 asserts req0# and expects gnt0# from an external arbiter. ro ? 6 locked transaction enable the pci lock# ball is ignored. 1 = locked transactions are propagated through the pex 8111 from the primary to secondary bus rw 0 7 m66en reflects the m66en ball state. when low, the pex 8111 pci bus is operating at 33 mhz. when high, the pex 8111 pci bus is operating at 66 mhz. ro 0 15:8 pci-to-pci express retry count valid only when the pci express link is down. determines the number of times to retry a pci type 1 configuration transaction to pci e xpress before aborting the transfer (in units of 2 14 retries). 0h = indicates that the tran saction is retried forever 255 = selects a retry count of 2 24 when the timer times out, a master abort is returned to the pci bus. rw 80h 23:16 pci express-to-pci retry count determines the number of times to retry a pc i express-to-pci transaction before aborting the transfer (in units of 2 4 retries). 0h = indicates that the tran saction is retried forever 255 = selects a retry count of 2 24 rw 0h
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 229 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 24 memory read line enable 0 = pex 8111 issues a memory read command for transactions that do not start on a cache boundary. 1 = memory read line command is issued when a transaction is not aligned to a cache boundary in prefetchable address space, and the bu rst transfer size is at least one cache line of data. the pci burst is stopped at the cach e line boundary when the burst transfer size is less than one cache line of data or when a memory read multiple command is started. rw 1 25 memory read multiple enable 0 = pex 8111 issues a memory read command for transactions that start on a cache boundary. 1 = memory read multiple command is issued when a transaction is aligned to a cache boundary in prefetchable address space, and the bu rst transfer size is at least one cache line of data. the pci burst continues when the burst transfer size remains greater than or equal to one cache line of data. rw 1 26 early byte enables expected 0 = pex 8111 expects pci bytes enables to be valid after irdy# is asserted 1 = pex 8111 expects the pci byte enables to be valid in the clock tick following the address phase for maximum compatibility wi th non-compliant pci devices, clear this bit to 0. for maximum performance, set this bit to 1. rw 0 29:27 programmed prefetch size valid only for memory read line and memory read multiple transactions, or memory read transactions accessing prefetchable memory space with the device-specific control register blind prefetch enable bit set. determines the number of bytes re quested from the pci express in terface as a result of a pci- to-pci express read. if a prefetch size is spec ified, the cache line boundary requirements of the memory read line and memory read multi ple commands are disabled and the number of bytes requested will match the prefetch size. enable feature only when the pci initiator re ads all requested data without disconnecting. otherwise, performance is impacted. the prefetch size is limited by the pci express device control register maximum read request size field. 000b = disabled 001b = 64 bytes 010b = 128 bytes 011b = 256 bytes 100b = 512 bytes 101b = 1,024 bytes 110b = 2,048 bytes 111b = 4,096 bytes (4 kb; refer to note) note: if the programmed prefetch size is 4 kb, the tlp controller configuration 0 register limit completion flow control credit bit must be set. rw 000b 31:30 reserved rsvdp 00b register 16-70. (offset 100ch; pcictl) pci control (cont.) bit(s) description access default
reverse bridge mode configuration registers plx technology, inc. 230 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-71. (offset 1014h; pciirqenb) pci interrupt request enable bit(s) description access default 0 serial eeprom done interrupt enable 1 = enables a pci interrupt to be generated when a serial eeprom read or write transaction completes note: refer to section 5.2, ?reverse bridge pci interrupts,? for further details. rw 0 1 gpio interrupt enable 1 = enables a pci interrupt to be generated wh en an interrupt is active from one of the gpio balls rw 0 2 reserved rsvdp 0 3 pci express-to-pci re try interrupt enable 1 = enables a pci interrupt to be generated when the pci express- to-pci retry count is reached rw 0 4 mailbox 0 interrupt enable 1 = enables a pci interrupt to be generated when mailbox 0 is written rw 0 5 mailbox 1 interrupt enable 1 = enables a pci interrupt to be generated when mailbox 1 is written rw 0 6 mailbox 2 interrupt enable 1 = enables a pci interrupt to be generated when mailbox 2 is written rw 0 7 mailbox 3 interrupt enable 1 = enables a pci interrupt to be generated when mailbox 3 is written rw 0 8 unsupported request interrupt enable 1 = enables a pci interrupt to be generated when an unsupported request completion response is received from the pci express rw 0 30:9 reserved rsvdp 0h 31 pci internal interrupt enable 1 = enables a pci interrupt to be generated as a result of an internal pex 8111 interrupt source note: refer to section 5.2, ?reverse bridge pci interrupts,? for further details. rw 1
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 231 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-72. (offset 1018h; irqstat) interrupt request status bit(s) description access default 0 serial eeprom done interrupt set when a serial eeprom read or write transaction completes. writing 1 clears this status bit. rw1c 0 1 gpio interrupt conveys the interrupt status for the four gpio balls. set i ndependently of the gpio interrupt enable bits. this bit is an or of the four individual gp io status bits. 1 = general-purpose i/o status register is read to determine the cause of the interrupt ro 0 2 reserved rsvdp 0 3 pci express-to-pci retry interrupt set when the pci express-to-pci retry count is reached. writing 1 clea rs this status bit. rw1c 0 4 mailbox 0 interrupt set when mailbox 0 is written. writing 1 clears this bit. rw1c 0 5 mailbox 1 interrupt set when mailbox 1 is written. writing 1 clears this bit. rw1c 0 6 mailbox 2 interrupt set when mailbox 2 is written. writing 1 clears this bit. rw1c 0 7 mailbox 3 interrupt set when mailbox 3 is written. writing 1 clears this bit. rw1c 0 8 unsupported request interrupt set when an unsupported request completion is received from the pci express interface, provided that the pci interrupt request enable register unsupported request interrupt enable bit is set. rw1c 0 31:9 reserved rsvdz 0h
reverse bridge mode configuration registers plx technology, inc. 232 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-73. (offset 1020h; gpioctl) general-purpose i/o control bit(s) description access default 0 gpio0 data when programmed as an output, values writte n to this bit appear on the gpio0 ball. reading this bit returns the value that was previously written. when programmed as an input, reading this b it returns the value present on the gpio0 ball. rw 0 1 gpio1 data when programmed as an output, values writte n to this bit appear on the gpio1 ball. reading this bit returns the value that was previously written. when programmed as an input, reading this b it returns the value present on the gpio1 ball. rw 0 2 gpio2 data when programmed as an output, values writte n to this bit appear on the gpio2 ball. reading this bit returns the value that was previously written. when programmed as an input, reading this b it returns the value present on the gpio2 ball. rw 0 3 gpio3 data when programmed as an output, values writte n to this bit appear on the gpio3 ball. reading this bit returns the value that was previously written. when programmed as an input, reading this b it returns the value present on the gpio3 ball. rw 0 4 gpio0 output enable the gpio diagnostic select field overrides this bit when a diagnostic output is selected. 0 = gpio0 ball is an input 1 = gpio0 ball is an output rw 1 5 gpio1 output enable the gpio diagnostic select field overrides this bit when a diagnostic output is selected. 0 = gpio1 ball is an input 1 = gpio1 ball is an output rw 0 6 gpio2 output enable the gpio diagnostic select field overrides this bit when a diagnostic output is selected. 0 = gpio2 ball is an input 1 = gpio2 ball is an output rw 0 7 gpio3 output enable the gpio diagnostic select field overrides this bit when a diagnostic output is selected. 0 = gpio3 ball is an input 1 = gpio3 ball is an output rw 0 8 gpio0 interrupt enable 1 = changes on the gpio0 ball (when programmed as an input) are enabled to generate an interrupt rw 0 9 gpio1 interrupt enable 1 = changes on the gpio1 ball (when programmed as an input) are enabled to generate an interrupt rw 0 10 gpio2 interrupt enable 1 = changes on the gpio2 ball (when programmed as an input) are enabled to generate an interrupt rw 0 11 gpio3 interrupt enable 1 = changes on the gpio3 ball (when programmed as an input) are enabled to generate an interrupt rw 0
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 233 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 13:12 gpio diagnostic select selects diagnostic signals that are output on the gpio balls. 00b = normal gpio operation 01b = gpio0 driven high when link is up. gpio [3:1] operate according to the configuration specified by bits [7:5] of this register 10b = gpio[3:0] driven with lower four bits of the ltssm state machine for 2 seconds, alternating with gpio[1:0] driven with the uppe r two bits of the ltssm state machine for 1s 11b = gpio[3:0] driven with pmu linkstate (l2, l1, l0s, and l0) ltssm codes 00h ? l3_l2 (fundamental reset) 01h ? detect 02h ? polling.active 03h ? polling.configuration 04h ? polling.compliance 05h ? configuration.linkw idth.start & accept 06h ? configuration.la nenum.wait & accept 07h ? configuration.complete 08h ? configuration.idle 09h ? reserved 0ah ? reserved 0bh ? reserved 0ch ? reserved 0dh ? reserved 0eh ? l0 0fh ? l0 (transmit e.i.ordered-set) 10h ? l0 (wait e.i.ordered-set) 12h ? l1.idle 14h ? l2.idle 15h ? recovery.rcvrlock (extended sync enabled) 16h ? recovery.rcvrlock 17h ? recovery.rcvrcfg 18h ? recovery.idle 19h ? disabled (transmit ts1) 1ah ? disabled (trans mit e.i.ordered-set) 1dh ? disabled (wa it electrical idle) 1eh ? disabled (disable) 1fh ? loopback.entry 20h ? loopback.active 21h ? loopback.exit 22h ? hot reset (wait ts1 with hot reset) 23h ? hot reset (reset active) 24h ? loopback.actice (tra nsmit e.i.ordered-set) 25h ? loopback.active (w ait electri cal idle) rw 01b 31:14 reserved rsvdp 0h register 16-73. (offset 1020h; gpioctl) general-purpose i/o control (cont.) bit(s) description access default
reverse bridge mode configuration registers plx technology, inc. 234 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-74. (offset 1024h; gpiostat) general-purpose i/o status bit(s) description access default 0 gpio0 interrupt set when the gpio0 ball state ch anges and the ball is programm ed as an input. writing 1 clears this bit. rw1c 0 1 gpio1 interrupt set when the gpio1 ball state ch anges and the ball is programm ed as an input. writing 1 clears this bit. rw1c 0 2 gpio2 interrupt set when the gpio2 ball state ch anges and the ball is programm ed as an input. writing 1 clears this bit. rw1c 0 3 gpio3 interrupt set when the gpio3 ball state ch anges and the ball is programm ed as an input. writing 1 clears this bit. rw1c 0 31:4 reserved rsvdz 0h register 16-75. (offset 1030h; mailbox0) mailbox 0 bit(s) description access default 31:0 mailbox data written or read from the pci express or pci bus. interrupts are generated to the pci express interface or pci bus when this register is written. rw feedfaceh register 16-76. (offset 1034h; mailbox1) mailbox 1 bit(s) description access default 31:0 mailbox data written or read from the pci express or pci bus. interrupts are generated to the pci express interface or pci bus when this register is written. rw 0h register 16-77. (offset 1038h; mailbox2) mailbox 2 bit(s) description access default 31:0 mailbox data written or read from the pci express or pci bu s. interrupts are generated to the pci express interface or pci bus when this register is written. rw 0h register 16-78. (offset 103ch; mailbox3) mailbox 3 bit(s) description access default 31:0 mailbox data written or read from the pci express or pci bu s. interrupts are generated to the pci express interface or pci bus when this register is written. rw 0h
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 235 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 note: chiprev is the silicon revision, encoded as a 4-digit bcd value. the chiprev value for the third release of the chip (rev. bb) is 0201h. the least-significant digit is incremented for mask changes, and the most-significant digit is incremented for major revisions. register 16-79. (offset 1040h; chiprev) chip silicon revision bit(s) description access default 15:0 chip revision returns the pex 8111 current silicon revision number. ro current revision 31:16 reserved rsvdp 0h register 16-80. (offset 1044h; diagctl) diagnostic control ( factory test only ) bit(s) description access default 0 fast times factory test only. rw 0 1 force pci interrupt 1 = forces the pci int x # interrupt signal to assert. the pci interrupt pin register determines which int x # signal is asserted. effective only when the pci command register interrupt disable bit is low. rw 0 2 force pci serr 1 = forces the pci serr# interrupt signal to assert when the pci command register serr# enable bit is set rw 0 3 force pci express interrupt 1 = forces an interrupt to the pci express ro ot complex, using mess age signaled interrupts or virtual int x # interrupts rw 0 31:4 reserved rsvdp 0h
reverse bridge mode configuration registers plx technology, inc. 236 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-81. (offset 1048h; tlpcfg0) tlp controller configuration 0 bit(s) description access default 7:0 cfg_num_fts forced num_fts signal. num_f ts represents the number of fast training sequence (0 to 255). refer to the pci express r1.0a , section 4.2.4.3, fo r detailed information. rw 20h 8 cfg_ack_fmode pci express interface ack_dllp transmitting interval mode. 0 = pci express interface uses own interval value 1 = pci express interface uses cfg_ack_count as interval value rw 0 9 cfg_to_fmode pci express interface timeout de tection mode for replay timer. 0 = pci express interface uses own timer value 1 = pci express interface uses cfg_to_count as timer value rw 0 10 cfg_port_disable 1 = serdes in the pci express in terface is disabled. this allo ws the endpoint to disable the pci express connection when powered up or before the configuration is completed. rw 0 11 cfg_rcv_detect set when the pci express interface establishes the pci express connection. ro 0 12 cfg_lpb_mode link loop-back mode. 1 = pex 8111 changes its ltssm state to the loop- back state, becomes the loop-back master, and starts transmitting pack ets of pseudo random numbers rw 0 13 cfg_port_mode 0 = link pci express interface is confi gured as an upstream port (endpoint) 1 = link pci express interface is configur ed as a downstream port (root complex) rw 1 14 reserved rsvdp 0 15 cfg_ecrc_gen_enable 1 = link is allowed generate ecrc the pex 8111 does not support ecrc; theref ore, this bit is cleared to 0. rw 0
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 237 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 16 tlp_cpld_nosuccess_malform_enable 0 = received completion is retained 1 = completion received when completion timeout expired is treated as a malformed tlp and discarded rw 1 17 scrambler disable 0 = data scrambling is enabled. 1 = data scrambling is disabled. set only when test ing and debugging. rw 0 18 delay link training 0 = link training is allowed to commence immediately after pc irst# is de-asserted 1 = link training is delayed for 12 ms after pcirst# is de-asserted when gpio3 is low at the trailing edge of reset , this bit is automatically set. because this bit is used during link training, it must be set by driving gpio3 low during pcirst# assertion. rw 0 19 decode primary bus number 0 = pex 8111 ignores the primary bus number in a pci express type 0 configuration request. 1 = pex 8111 compares the primary bus number in a pci express type 0 configuration request with the primary bus number register. when they match, the request is accepted. otherwise, an unsupported request is returned . this comparison occurs only after the first type 0 configuration write occurs. rw 0 20 ignore function number 0 = pex 8111 only responds to function number 0 during a type 0 configuration transaction. accesses to other function numbers result in an unsupported request (pci express) or master abort (pci). 1 = pex 8111 ignores the function number in a pci or pci express type 0 configuration request, and responds to all eight functions. rw 0 21 check rcb boundary 0 = pex 8111 ignores read completion boundary (rcb) violations 1 = pex 8111 checks for rcb violations. when de tected, the pex 8111 treats it as a malformed tlp (packet is dropped and a non-fa tal error message is transmitted) rw 0 22 limit completion flow control credit 0 = pex 8111 advertises infinite fl ow control credits for completions 1 = pex 8111advertises completion flow control credits, based on available buffer storage must be set when the pci control register programmed prefetch size field is set to 4 kb. when gpio2 is low at the trailing edge of pcirst#, this bit is automatically set. because this bit is used during link training, it must be set by driving gpio2 low during pcirst# assertion. rw 0 23 l2 secondary bus reset when clear and the pex 8111 remains in th e l2/l3 ready state, pci-to-pci express configuration transactions are retried until the pci control register pci-to-pci express retry count expires. the pex 8111 responds with a master abort. when set, and the pex 8111 remains in the l2/l3 ready state, pci-to-pci express configuration transactions result in a secondary bus reset. af ter the link training completes, the pci-to-pci express configurati on transaction completes normally. rw 1 31:24 reserved rsvdp 0h register 16-81. (offset 1048h; tlpcfg0) tlp controller configuration 0 (cont.) bit(s) description access default
reverse bridge mode configuration registers plx technology, inc. 238 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-82. (offset 104ch; tlpcf g1) tlp controller configuration 1 bit(s) description access default 20:0 cfg_to_count pci express interface replay timer timeout value when cfg_to_fmode is set to 1. rw d4h 30:21 cfg_ack_count pci express interface ack dllp transmitting interval value when cfg_ack_fmode is set to 1. rw 0h 31 reserved rsvdp 0 register 16-83. (offset 1050h; tlpcfg2) tlp controller configuration 2 bit(s) description access default 15:0 cfg_completer_id0 bits [15:8] = bus number bits [7:3] = device number bits [2:0] = function number the bus, device, and function numbers of a configuration transaction to the pex 8111 are latched in this register. the latched values are then used when generating the completion. rw 0h 26:16 update credit fc controls a counter that determines the gap between updatefc dllps (in units of 62.5 mhz clocks = 16 ns = 4 symbol time s). when data or headers are read from the tlp controller, the credit allocation manager tr ansmits a set of updatefc dl lps; posted, non-posted, and completion when the tlp controller configuration 0 register limit completion flow control credit bit is set. while transmitting the set of dllps, the credit allocation manager uses the counter value to in sert gaps between the dllps. the bus, device, and function numbers of a configuration transaction to the pex 8111 are latched in this register. the latched values are then used when generating the completion. rw 1h 31:27 reserved rsvdp 0h register 16-84. (offset 1054h; tlptag) tlp controller tag bit(s) description access default 7:0 tag bme1 message request tag field. rw 0h 15:8 tag erm error manager tag field. rw 0h 23:16 tag pme power manager tag field. rw 0h 31:24 reserved rsvdp 0h
june, 2006 main control registers pex 8111bb expresslane pci express-to-pci bridge data book 239 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 register 16-85. (offset 1058h; tlptimelimit0) tlp controller time limit 0 bit(s) description access default 23:0 bme_completion_timeout_limit bus master engine completion timeout (i n pci clock units). the default value produces a 10-ms timeout. rw 51615h (m66en low) a2c2ah (m66en high) 27:24 l2l3_pwr_removal_time_limit determines length of time before power is removed after entering the l2 state. value to be at least 100 ns. contains pci clock units. rw 4h (m66en low) 8h (m66en high) 31:28 reserved rsvdp 0h register 16-86. (offset 105ch; tlptime limit1) tlp controller time limit 1 bit(s) description access default 10:0 aspm_li_dllp_interval_time_limit determines time interval between two consecutive pm_active_state_request_l1 dllp tr ansmissions. the de fault is 10 s for both 14dh and 29ah. allow at least 10 s spent in ltssm l0 and l0s state before the next pm_active_state_request_l1 dllp is transmitted. refer to the pci express r1.0a errata, page 19, for detailed information. contains pci clock units. rw 14dh (m66en low) 29ah (m66en high) 31:11 reserved rsvdp 0h register 16-87. (offset 1064h; ecfga ddr) enhanced configuration address bit(s) description access default 11:0 reserved rsvdp 0h 14:12 configuration function number provides the function number for an enhanced configuration transaction. rw 000b 19:15 configuration device number provides the device number for an enhanced configuration transaction. rw 0h 27:20 configuration bus number provides the bus number for an enhanced configuration transaction. rw 0h 30:28 reserved rsvdp 000b 31 enhanced configuration enable 0 = accesses to the base address 0 register, offset 2000h, are not responded to by the pex 8111 1 = accesses to the base address 0 register, offset 2000h, are forwarded to the pci express interface as a configuration request rw 0
reverse bridge mode configuration registers plx technology, inc. 240 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 241 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 17 shared memory 17.1 overview the pex 8111 contains a 2 kb x 32-bit (8-kb) memory block that is accessed from the serial eeprom, pci express interface, or pci bus. 17.2 serial eeprom accesses when the shared memory load bit in the serial eeprom format byte is set, the shared memory is loaded from the serial eeprom st arting at location reg byte count + 6. the number of bytes to load is determined by the value in serial eeprom locations reg byte count + 4 and reg byte count + 5. the serial eeprom data is always loaded into the shared memory starting at address 0. data is transferred from the serial eeprom to th e shared memory (in units of dwords). (refer to chapter 6, ?serial eeprom controller,? for details.) 17.3 pci express accesses the shared memory is accessed using th e 64-kb address space defined by the base address 0 register. the shared memory is located at offset 8000h in th is space. pci express posted writes are used to write data to the shared memory. singl e or burst writes are accepted, and pci express first and last byte enables are supported. when shared memory write data is poisoned, the data is discarded and an err_nonfatal message is generated (when enabled). pci express non-posted reads are used to read data from the shared memo ry. single or burst reads are accepted. when the 8-kb address boundary space of the shared memory is reached during a burst write or read, the address wraps around to the start of memory. 17.4 pci accesses the shared memory is accessed using th e 64-kb address space defined by the base address 0 register. the shared memory is located at address offset 8000h in this space. pci single or burst writes are used to write data to the shared memory. pci byte en ables are supported for each dword transferred. pci single or burst reads are used to read data from the shared memory . when the 8-kb address boundary space of the shared memory is reached during a burs t write or read, a pci disconnect is generated.
shared memory plx technology, inc. 242 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 243 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 18 testability and debug 18.1 jtag interface the pex 8111 provides a joint test action group (jta g) boundary scan interface, which is utilized to debug board connectiv ity for each ball. 18.1.1 ieee standard 1149.1 test access port the ieee standard 1149.1 test access port (tap), commonly referred to as the jtag debug port, is an architectural standard described in the ieee standard 1149.1-1990 ieee standard test access port and boundary-scan architecture . this standard describes a met hod for accessing internal pex 8111 facilities, using a four- or five-signal interface. the jtag debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. the enhancements, which comply with the ieee standard 1149.1b-1994 specifications for vendor-specific extensions , are compatible with sta ndard jtag hardware for boundary-scan system testing. jtag signals ? jtag debug port implements the four required jtag signals (tck, tdi, tdo, tms) and the optional trst# signal jtag clock requirements ? tck signal frequency range from dc to 10 mhz jtag reset requirements ? refer to section 18.1.4, ?jtag reset input trst#?
testability and debug plx technology, inc. 244 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 18.1.2 jtag instructions table 18-1 delineates the ieee standard 1149.1 extest, idcode, sample/preload, bypass, and private instructions, provided by the jtag debug port, and their input codes. private instructions are for plx use only. invalid instructions behave as the bypass instruction. table 18-2 delineates the idcode values returned by the pex 8111. table 18-1. extest, idcode, sample/pre load, bypass, and private instructions instruction input code comments extest 00000b ieee standard 1149.1-1990 idcode 00001b sample/preload 00011b bypass 11111b private a a. warning: non-plx use of private instructions can cause the pex 8111 to operate in a hazardous manner. 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b table 18-2. pex 8111 jtag idcode values pex 8111 version part number plx manufacturer identity least significant bit bits 0010b 1000_0001_1101_0010b 000_0001_0000b 1 hex 2h 81d2h 10h 1h decimal 2 33234 16 1
june, 2006 jtag boundary scan pex 8111bb expresslane pci express-to-pci bridge data book 245 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 18.1.3 jtag boundary scan scan description language (bsdl), ieee 1149.1b-1994 , is a supplement to ieee standard 1149.1- 1990 and ieee 1149.1a-1993, ieee standard test access port and boundary-scan architecture. bsdl , a subset of the ieee 1076-1993 standard vhsic hardware description language (vhdl) , which allows a rigorous description of testability features in components that comply with the standard. it is used by automated test pattern generation tools for package interconnect tests and electronic design automation (eda) tools for synthesized test logic and verification. bsdl supports robust extensions that are used for internal test generation and to write software for hardware debug and diagnostics. the primary components of bsdl include the logical port description, physical ball map, instruction set, and boundary register description. the logical port description assigns symbolic names to the pex 8111 balls. each ball contains a logical type of in, out, in out, buffer, or linkage th at defines the logical direction of signal flow. the physical ball map correlates the pex 8111 logical ports to the physical balls of a specific package. a bsdl description has several physical ball maps; each map is assigned a unique name. instruction set statements describe the bit patterns that must be shifted into the instruction register to place the pex 8111 in the various test modes defined by the standard. instruct ion set statements also support descriptions of instructions that are unique to the pex 8111. the boundary register description lists each cell or shift stage of the boundary register. each cell contains a unique number; the cell nu mbered 0 is the closest to the test data out (tdo) ball and the cell with the highest number is closest to the test da ta in (tdi) ball. each cell contains additional information, including: cell type logical port associated with the cell logical function of the cell safe value control cell number disable value result value 18.1.4 jtag reset input trst# the trst# input ball is the asynchronous jtag logic reset. when trst# is asserted, it causes the pex 8111 tap controller to initialize. in addition, when the tap controller is initialized, it selects the pex 8111 normal logic path (pci express interface-to-i/o). it is recommended that the following be taken into consideration when implementing the asynchronous jtag logic reset on a board: if jtag functionality is required, consider one of the following: ? trst# input signal uses a low-to-high trans ition one time during the pex 8111 boot-up, along with the rst# signal ? hold the pex 8111 tms ball high while transitioning the pex 8111 tck ball five times if jtag functionality is not required, the trst # signal must be direct ly connected to ground
testability and debug plx technology, inc. 246 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 247 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 19 electrical specifications 19.1 power sequence the power supply for the pex8111bb i/o buffers are 3.3v ( vdd3.3 and vddq ) and core is 1.5v ( vdd1.5 , vdd_p , vdd_r , vdd_t , and av d d ). to fully comply with pci r2.2 or pci r3.0 , a third power supply for vio ( vdd5 ) is also supported. vio connects to a cathode of the high clamp diode in the pci buffers. in a 5v system, set vio to 5v, and in a 3.3v system, set to 3.3v. as in all multi-supply devices, ensure proper power-on procedures. table 19-1 specifies the recommended pex 8111 power-on and power-down se quences. if the sequences cannot be guaranteed, it is recommended that each power supply be turn ed-on/turned-off within 10 ms of one another. caution: exposure to sequences other than those recommended ca n affect reliability. 19.1.1 vio if the vio voltage source is not powered and it presents a low-impedance path to ground, the pex 8111?s vio balls can source high current, wh ich could immediately damage the pex 8111 or cause it undue long-term electrical st ress. the amount of cu rrent each pci ball/pad sources is dependent upon the device that is driving the signal/pad, or the value of the pull-up resistor when the signal is not driven. for designs and add-in boards that have an indepe ndent voltage source for vio, for which proper power sequencing cannot be guaranteed, a resistor is st rongly recommended between the vio voltage source and pex 8111 vio balls ( vdd5 ) to limit the current and protect the devices from damage or long-term undue stress. use the following guidelines to determine the value of this required resistance: 3.3v signaling environments ? 40 to 200-ohm resistance between the vio voltage source and the pex 8111 vio balls is recommended if vio is a maximum of 3.6 v 3.3 or 5v signaling environments ? 40 to 70-ohm resistance is recommended a single resistor can be used if the vio balls are bused, or multiple parallel resistors can be used between the vio voltage source and vio balls. the resistor power dissipation rating depends upon the resistance size and signaling environment. for example , if a single 50-ohm resistor is used in a 5v-signaling environment, the worst-case power dissipation can result in 480 mw , calculated as follows: if four, 200-ohm resistors are used in para llel, each is required to dissipate 120 mw. table 19-1. power sequence power-on sequence power-down sequence 1. vdd5 1. 1.5v 2. 3.3v 2. 3.3v 3. 1.5v 3. vdd5 480 mw = (v * v)/r (5.5v (maximum signal amplitude, plus 10%) ? 0.6v (1 diode drop)) 2 50 ohms
electrical specifications plx technology, inc. 248 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 any resistance value within the recommended rang es prevents damage to the pex 8111, while providing sufficient clamping action to hold the input voltage (vin) below its maximum rating. a resistance value at the lower end of the range is recommended to provide pr eferable clamping action, and a sufficient vin margin. 19.2 absolute maximum ratings caution: conditions that exceed the absolute maxi mum limits can de stroy the pex 8111. table 19-2. absolute maximum ratings symbol parameter conditions min max unit vdd1.5 , vdd_p , vdd_r , vdd_t , avdd 1.5v power supply voltages with respect to ground -0.5 +1.8 v vdd3.3 , vddq 3.3v power supply voltages -0.5 +4.6 v vdd5 5v power supply voltage -0.5 +6.6 v v i dc input voltage 3.3v buffer -0.5 +4.6 v 5v tolerant buffer (pci) -0.5 +6.6 v i out dc output current, per ball 3 ma buffer -10 +10 ma 6 ma buffer -20 +20 ma 12 ma buffer -40 +40 ma 24 ma buffer (pci) -70 +70 ma t stg storage temperature no bias -65 +150 c v esd esd rating r = 1.5k, c = 100 pf ? 2 kv table 19-3. package thermal resistance package theta jc (c/w) 0 m/s theta ja (c/w) 0 m/s 13-mm square 144-ball pbga 6.8 32.4 10-mm square 161-ball fbga 10.62 45.3
june, 2006 recommended operating conditions pex 8111bb expresslane pci express-to-pci bridge data book 249 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 19.3 recommended operating conditions caution: conditions that exceed the operating limits can cause the pex 8111 to malfunction. table 19-4. recommended operating conditions symbol parameter conditions min max unit vdd1.5 , vdd_p , vdd_r , vdd_t , av d d 1.5v power supply voltages 1.4 1.6 v vdd3.3 , vddq 3.3v power supply voltages 3.0 3.6 v vdd5 5v power supply voltage note 1 4.75 5.25 v v n negative trigger voltage 3.3v buffer 0.8 1.7 v 5v tolerant buffer (pci) 0.8 1.7 v v p positive trigger voltage 3.3v buffer 1.3 2.4 v 5v tolerant buffer (pci) 1.3 2.4 v v il low level input voltage 3.3v buffer 0 0.7 v 5v tolerant buffer (pci) 0 0.8 v v ih high level input voltage 3.3v buffer 1.7 vdd3.3 v 5v tolerant buffer (pci) 2.0 vdd5 + 0.5 v i ol low level output current 3 ma buffer (v ol = 0.4) 3ma 6 ma buffer (v ol = 0.4) 6ma 12 ma buffer (v ol = 0.4) 12 ma 24 ma buffer (v ol = 0.4) (pci) 24 ma i oh high level output current 3 ma buffer (v oh = 2.4) -3 ma 6 ma buffer (v oh = 2.4) -6 ma 12 ma buffer (v oh = 2.4) -12 ma 24 ma buffer (v oh = 2.4) (pci) -24 ma t a operating temperature 0 70 c t r input rise times normal input 0 200 ns t f input fall time 0 200 ns t r input rise times schmitt input 010ms t f input fall time 0 10 ms notes: 1. in a 3.3v-only system, the vdd5 balls can be connected to the 3.3v power supply (3.0 to 3.6v). 2. v il and v ih for non-pci buffered inputs, such as, jtag, gpio , and serial eeprom signals and strapping signals (extarb, fwd, and so forth), are 3.3v lvttl inputs (cmos) v il = 0.8v maximum and v ih = 2v minimum.
electrical specifications plx technology, inc. 250 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 19.4 dc specifications operating conditions ? vdd1.5 = 1.5v 0.1v, vdd3.3 = 3.3v 0.3v, t a = 0 to 70c typical values ? vdd1.5 = 1.5v, vdd3.3 = 3.3v, t a = 25c 19.4.1 pci bus dc specification operating conditions ? vdd1.5 = 1.5v 0.1v, vdd3.3 = 3.3v 0.3v, t a = 0 to 70c typical values ? vdd1.5 = 1.5v, vdd3.3 = 3.3v, t a = 25c table 19-5. pci express interface dc specifications symbol parameter conditions min typ max unit i vdd1.5 vdd1.5 supply current vdd1.5 = 1.5v 180 207 ma i vddserdes vdd_p, vdd_r, vdd_t, avdd supply currents vdd_p , vdd_r , vdd_t , avdd = 1.5v i vdd3.3 vdd3.3 supply current vdd3.3 = 3.3v 19 22 ma i vddq vddq supply current vddq = 3.3v i vdd5 vdd5 supply current vdd5 = 5.0v .003 .004 ma notes: 1. i vdd1.5 + i vddserdes = 207 ma. 2. i vdd3.3 + i vddq = 22 ma. table 19-6. pci bus dc specification symbol parameter conditions min typ max unit v ihd pci 3.3v input high voltage 0.5 * vdd3.3 vdd3.3 v v ild pci 3.3v input low voltage 0 0.7 v v ih pci 5.0v input high voltage 2.0 5.5 v v il pci 5.0v input low voltage 0 0.8 v i il input leakage 0v < v in < vdd5 -10 +10 a i oz hi-z state data line leakage 10 a v oh3 pci 3.3v output high voltage i out = -500 a 0.9 * vdd3.3 v v ol3 pci 3.3v output low voltage i out = 1500 a 0.1 * vdd3.3 v v oh pci 5.0v output high voltage i out = -12 ma 2.4 v v ol pci 5.0v output low voltage i out = 12 ma 0.4 v c in input capacitance ball to gnd 10 pf c clk clk ball capa citance 5 12 pf c idsel idsel ball capacitance 8 pf
june, 2006 serdes interface dc characteristics pex 8111bb expresslane pci express-to-pci bridge data book 251 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 19.4.2 serdes interface dc characteristics table 19-7. pci bus dc specification item conditions min typ max unit tx i/o characteristics differential output amplitude 0.85 1.01 1.02 v emphasis levels 3.25 3.61 3.76 db tx eye width 0.85 0.92 0.96 ui a a. ui is unit interval. given a data stream of a repeating pattern of alternating 1 and 0 values, the unit interval is the value measured by averaging the time interval between voltage transitions, over a time interval long enough to make all intentional frequency modulation of the source clock negligible. maximum time between the jitter median and deviation from the median 0.02 0.03 0.07 ui tx rise time and fall time 0.19 0.27 0.40 ui rms ac common mode voltage 9.2 12.8 18.2 mv absolute delta of dc common mode voltage during l0 and electrical idle 0.5 25 97 mv absolute delta of dc common mode voltage between d+ and d- 0.7 8.8 16.9 mv electrical idle differential peak output voltage 2.35 4.81 9.0 mv the amount of voltage change allowed during receiver detection 401 460 484 mv tx dc common mode voltage 0.60 0.84 0.97 v tx short current 43.1 52.2 67.4 ma maximum time to transition to a valid electrical idle after transmitting an electrical idle order set 4.4 5.2 6.4 ui maximum time to transition to a valid tx specification after leaving an electrical idle condition 2.1 2.9 3.5 ui differential return loss 11.4 14.1 16.4 db common mode return loss 6.5 10.2 12.3 db dc differential tx impedance 95.2 107.6 116.9 ohm lane-to-lane output skew 115 167 215 ps rx i/o characteristics differential input amplitude 0.175 ? 3.3 v jitter tolerance rx data input amplitude = 175 mv sinusoidal jitter ? 0.256 ui backplane length ? 30 inches rx differential return loss 15.6 19.1 21.8 db rx common mode return loss 7.7 12.4 14.0 db dc differential input im pedance 92.7 107.0 115.8 ohm dc input impedance 45.0 53.2 57.5 ohm power down input impedance 361 3380 ? ohm electrical idle detect threshold 61 ? 173 mv
electrical specifications plx technology, inc. 252 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 figure 19-1. sig-test results
june, 2006 serdes interface dc characteristics pex 8111bb expresslane pci express-to-pci bridge data book 253 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 figure 19-2. near-end/far-end eye diagram
electrical specifications plx technology, inc. 254 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 19.5 ac specifications 19.5.1 serdes interface ac specification table 19-8. pex_refclk ac specifications symbol parameter test conditions min max unit notes pex_refclk 100-mhz differential reference clock input 100 mhz v cm input common-mode voltage 0.6 0.65 0.7 v clkin dc input clock duty cycle 40 50 60 % t r /t f input clock rise/fall times 0.2 rcui a a. rcui refers to the reference clock period (10 ns typical). v sw differential input voltage swing b b. ac coupling required. 0.6 1.6 v r term reference clock differential termination 110 ohms jt clk_ref input jitter (peak-to-peak) 0.1 ui
june, 2006 pci bus 33-mhz ac specifications pex 8111bb expresslane pci express-to-pci bridge data book 255 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 19.5.2 pci bus 33-mhz ac specifications operating conditions ? vdd1.5 = 1.5v 0.1v, vdd3.3 = 3.3v 0.3v, t a = 0 to 70c typical values ? vdd1.5 = 1.5v, vdd3.3 = 3.3v, t a = 25c table 19-9. pci bus 33-mhz ac specifications symbol parameter conditions min max unit notes t cyc pci clk cycle time 30 ns t va l clk to signal valid delay ? bused signals 2 11 ns 2 , 3 t va l (ptp) clk to signal valid delay ? point-to-point 2 12 ns 2 , 3 t on float to active delay 2 ns 7 t off active to float delay 28 ns 7 t su input setup to clk ? bused signals 6 ns 3 , 8 t su (ptp) input setup to clk ? point-to-point 10,12 ns 3 t h input hold from clk 0 ns t rst reset active time after power stable 1 ms 5 t rst-clk reset active time after clk stable 100 s 5 t rst-off reset active to output float delay 40 ns 5 , 6 , 7 t rhfa rst# high to first configuration access 2 25 clocks 9 t rhff rst# high to first frame# assertion 5 clocks notes: 2. for parts compliant to the 5v signaling environment: minimum times are evaluated with 0 pf equivalent load; ma ximum times are evaluated with 50 pf equivalent load. actual test capacitance varies; however, results must be correlated to these specifications. faster buffers can exhibit ring back when attached to a 50 pf lump load but should be of no consequence when the output buffers are in full compliance with slew rate and v/i curve specifications. for parts compliant to the 3.3v signaling environment: minimum times are evaluated with the same load used for sl ew rate measurement; maximu m times are evaluated with a parallel rc load of 25 ohms and 10 pf. 3. req# and gnt# are point-to-point signals and have different out put valid delay and input setup times than bused signals. the setup for req# is 12. the setup for gnt# is 10. all other signals are bused. 5. clk is stable when it meets the pci clk specifications. rst# is asserted and de-a sserted asynchronously with respect to clk. 6. all output drivers must be asynchr onously floated when rst# is active. 7. for active/float timing me asurement purposes, the hi-z or ?off? state is de fined as ?total current delivered through the pex 8111 ball is less than or equal to the leakage current specification.? 8. setup time applies only when the device is not driving the ball. devices cannot dr ive and receive signals at the same time. 9. at 33 mhz, the pex 8111 must be re ady to accept a confi guration access within 1s after rst# is high.
electrical specifications plx technology, inc. 256 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 19.5.3 pci bus 66-mhz ac specifications operating conditions ? vdd1.5 = 1.5v 0.1v, vdd3.3 = 3.3v 0.3v, t a = 0 to 70c typical values ? vdd1.5 = 1.5v, vdd3.3 = 3.3v, t a = 25c table 19-10. pci bus 66-mhz ac specifications symbol parameter conditions min max unit notes t cyc pci clk cycle time 15 ns t va l clk to signal valid delay ? bused signals 2 6 ns 3 , 8 t va l (ptp) clk to signal valid delay ? point-to-point 2 6 ns 3 , 8 t on float to active delay 2 ns 8 , 9 t off active to float delay 14 ns 9 t su input setup to clk ? bused signals 3 ns 3 , 10 t su (ptp) input setup to clk ? point-to-point 5 ns 3 t h input hold from clk 0 ns t rst reset active time after power stable 1 ms 5 t rst-clk reset active time after clk stable 100 s 5 t rst-off reset active to output float delay 40 ns 5 , 6 t rhfa rst# high to first co nfiguration access 2 25 clocks 9 t rhff rst# high to first frame# assertion 5 clocks notes: 3. req# and gnt# are point-to-point si gnals and have different input setup ti mes than bused signals. the setup for req# and gnt# is 5 ns at 66 mhz. all other signals are bused. 5. when m66en is asserted, clk is stable when it meets the requi rements in the pci r3.0, secti on 7.6.4.1. rst# is asserted and de-asserted asynchronously with resp ect to clk. refer to the pci r3.0, section 4.3.2, for further details. 6. all output drivers must be floated when rst# is active. 8. when m66en is asserted, the minimum sp ecification for tval(min), tval(ptp)(mi n), and ton are reduced to 1 ns when a mechanism is provided to guarantee a minimum value of 2 ns when m66en is de-asserted. 9. for active/float timi ng measurement purposes, the hi-z or ?off? state is defined as ?total current delivered through the pex 8111 ball is less than or equal to the leakage current specification.? 10. setup time applies only when the device is not driving the signal. devices cannot drive and receive signals at the same time . refer to the pci r3.0, section 3.10, item 9, for further details.
pex 8111bb expresslane pci express-to-pci bridge data book 257 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 chapter 20 physical specifications 20.1 pex 8111 package specifications the pex 8111 is offered in two package types: 13-mm square 144-ball pbga (plastic bga) package (refer to table 20-1 ) 10-mm square 161-ball fbga (fine- pitch bga) package (refer to table 20-2 ) table 20-1. pex 8111 144-ball pbga package specifications parameter specification package type plastic ball grid array package dimensions 13 x 13 mm (approximately 1.83 mm high) ball matrix pattern 12 x 12 mm ball pitch 1.00 mm ball diameter 0.60 0.15 mm ball spacing 0.40 mm table 20-2. pex 8111 161-ball fbga package specifications parameter specification package type fine-pitch ball grid array package dimensions 10 x 10 mm (approximately 1.43 mm high) ball matrix pattern 9 x 9 mm ball pitch 0.65 mm ball diameter 0.60 0.15 mm ball spacing 0.40 mm
physical specifications plx technology, inc. 258 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 20.2 mechanical drawings figure 20-1. 144-ball pbga mechanical drawing
june, 2006 mechanical drawings pex 8111bb expresslane pci express-to-pci bridge data book 259 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 figure 20-2. 161-ball fbga mechanical drawing
physical specifications plx technology, inc. 260 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 20.3 pcb layouts figure 20-3. 144-ball pbga pcb layout note: refer to the pex 8111 quick start design note for the trace lengths and a detailed description of the pci express layout considerations. des ign rule on board (general) bga land dia. : a=450um bga land pitch : p=1000um space btwn lands : b s = 550um line/space : l w /l s =100um/100um p a b s b s l s l w center of package p edge of package red : traces on an upper signal layer for the pcb blue : traces on a lower signal layer for pcb 2 signal layers are required due to routing only one trace between bga lands.
june, 2006 pcb layouts pex 8111bb expresslane pci express-to-pci bridge data book 261 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 figure 20-4. 161-ball fbga pcb layout note: refer to the pex 8111 quick start design note for the trace lengths and a detailed description of the pci express layout considerations.
physical specifications plx technology, inc. 262 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2
pex 8111bb expresslane pci express-to-pci bridge data book 263 copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 appendix a general information a.1 product ordering information contact your local plx sales representative for ordering information. table a-1. product ordering information part number description pex8111-bb66bc pci express-to-pci bridge, st andard bga package (144-ball, 13 x 13 mm) PEX8111-BB66FBC pci express-to-pci bridge, fi ne-pitch bga package (161-ball, 10 x 10 mm) pex8111-bb66bc f pci express-to-pci bridge, standa rd bga package (144-ball, 13 x 13 mm), lead free PEX8111-BB66FBC f pci express-to-pci bridge, fine-pit ch bga package (161-ball, 10 x 10 mm), lead free pex8111 -bb 66 fbc f f ? lead free i ? industrial temperature b ? plastic ball grid array package f ? fine pitch (161-ball package only) bb ? part revision code 66 ? speed grade (66 mhz pci bus) 8111 ? part number pex ? pci express product family pex8111rdk-f forward bridge reference design kit pex8111rdk-r reverse brid ge reference design kit
general information plx technology, inc. 264 pex 8111bb expresslane pci express-to-pci bridge data book copyright ? 2006 by plx technology inc. all rights reserved ? version 1.2 a.2 united states and international representatives and distributors plx technology, inc., representative s and distributors are listed at www.plxtech.com . a.3 technical support plx technology, inc., technical support information is listed at www.plxtech.com/support/ , or call 408 774-9060 or 800 759-3735.

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